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| MEC1404 Datasheet, PDF (224/572 Pages) Microchip Technology – Keyboard and Embedded Controller Products for Notebook PC | |||
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MEC140X/1X
13.12.4 SMI INTERRUPT MASK REGISTER
Offset Ch
MBX_ 03h
INDEX
Bits
Description
Type
7:1 EC_SWI_EN
R/W
EC Software Interrupt Enable. If this bit is â1bâ, the bit EC_WR in
the SMI Interrupt Source Register is enabled for the generation of
SIRQ or nSMI events.
0 EC_WR_EN
R
EC Mailbox Write.Interrupt Enable. Each bit in this field that is â1bâ
enables the generation of SIRQ interrupts when the corresponding
bit in the EC_SWI field in the SMI Interrupt Source Register is â1bâ.
Default
0h
Reset
Event
nSYSR
ST
0h
nSYSR
ST
DS00001956D-page 224
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