MEC1404 Datasheet, PDF (362/572 Pages) Microchip Technology – Keyboard and Embedded Controller Products for Notebook PC

MEC140X/1X
24.11.9 DMA CHANNEL N CRC DATA REGISTER
Offset ^24h
Bits
Description
Type
31:0 CRC
R/W
Writes to this register initialize the CRC generator. Reads from this
register return the output of the CRC that is calculated from the
data transfered by DMA Channel N. The output of the CRC gener-
ator is bit-reversed and inverted on reads, as required by the CRC-
32-IEEE definition.
A CRC can be accumulated across multiple DMA transactions on
Channel N. If it is necessary to save the intermediate CRC value,
the result of the read of this register must be bit-reversed and
inverted before being written back to this register.
Default
0h
Reset
Event
DMA_
RESET
24.11.10 DMA CHANNEL N CRC POST STATUS REGISTER
Offset ^28h
Bits
Description
31:4 Reserved
3 CRC_POST_TEST2
This is a test bit. Read back data is unpredictable.
Type
R
R
Default
-
0h
Reset
Event
-
DMA_
RESET
2 CRC_POST_TRANSFER
R
This bit is cleared to ‘0’ when a DMA transaction starts. If Post
Transfer is enabled, and the CRC is successfully transferred fol-
lowing the completion of the DMA transaction, this bit is set to ‘1’. If
the post transfer of the CRC is inhibited, because either firmware
or the device terminated the transaction, this bit remains ‘0’.
1 CRC_POST_TEST1
R
This is a test bit. Read back data is unpredictable.
0h
DMA_
RESET
0h
DMA_
RESET
0 CRC_POST_TEST0
This is a test bit. Read back data is unpredictable.
R
0h
DMA_
RESET
DS00001956D-page 362
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