MEC1404 Datasheet, PDF (427/572 Pages) Microchip Technology – Keyboard and Embedded Controller Products for Notebook PC

FIGURE 32-2:
BLOCK DIAGRAM OF TFDP DEBUG PORT
MEC140X/1X
Data
Register
PARALLEL-TO-SERIAL
CONVERTER
TFDP_DAT
WRITE_COMPLETE
CLOCK/CONTROL
INTERFACE
TFDP_CLK
The firmware executing on the embedded controller writes to the Debug Data Register to initiate a transfer cycle (). At
first, data from the Debug Data Register is shifted into the LSB. Afterwards, it is transmitted at the rate of one byte per
transfer cycle.
Data is transferred in one direction only from the Debug Data Register to the external interface. The data is shifted out
at the clock edge. The clock edge is selected by the EDGE_SEL bit in the Debug Control Register. After being shifted
out, valid data is guaranteed at the opposite edge of the TFDP_CLK. For example, when the EDGE_SEL bit is ‘0’
(default), valid data is provided at the falling edge of TFDP_CLK. The Setup Time (to the falling edge of TFDP_CLK) is
10 ns, minimum. The Hold Time is 1 ns, minimum.
When the Serial Debug Port is inactive, the TFDP_CLK and TFDP_DAT outputs are ‘1.’ The EC Bus Clock clock input
is the transfer clock.
FIGURE 32-3:
DATA TRANSFER
TFDP_CLK
TFDP_DAT
CPU_CLOCK
D0
D1
D2
D3
D4
D5
D6
D7
32.11 EC-Only Registers
The registers listed in the EC-Only Register Summary table are for a single instance of the Trace FIFO Debug Port
(TFDP). The addresses of each register listed in this table are defined as a relative offset to the host “Base Address”
defined in the EC-Only Register Base Address Table.
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DS00001956D-page 427