MEC1404 Datasheet, PDF (420/572 Pages) Microchip Technology – Keyboard and Embedded Controller Products for Notebook PC

MEC140X/1X
31.10 Description
FIGURE 31-2:
BC-LINK MASTER BLOCK DIAGRAM
BC_ERR
BC_BUSY_CLR
EC IF
Registers
BC Status / Control
Register
BC Address
Register
BC Data
Register
Clock
Divider
Bits
MCLK=48MHz Ring Oscillator
MCLK/2
MCLK/4
Clock
Generator
MCLK/8



MCLK/
Divider



MCLK/
63
BC Bus Master IP
External Pin interface
BCM_CLK
BCM_DAT
BCM_INT#
31.10.1 BC-LINK MASTER READ OPERATION
The BC-Link Read protocol requires two reads of the BC-Link Data Register. The two reads drive a two state-state
machine: the two states are Read#1 and Read#2. The Read#1 of the Data Register starts the read protocol on the BC-
Link pins and sets the BUSY bit in the BC-Link Status Register. The contents of the data read during Read#1 by the EC
is stale and is not to be used. After the BUSY bit in the BC-Link Status Register autonomously clears to ‘0’, the Read#2
of the Data Register transfers the data read from the peripheral/BC-Link companion chip to the EC.
1. Software starts by checking the status of the BUSY bit in the Status Register. If the BUSY bit is ‘0’, proceed. If
BUSY is ‘1’, firmware must wait until it is ‘0’.
2. Software writes the address of the register to be read into the BC-Link Address Register.
3. Software then reads the Data Register. This read returns random data. The read activates the BC-Link Master
state machine to transmit the read request packet to the BC-Link companion. When the transfer initiates, the
hardware sets the BUSY bit to a ‘1’.
4. The BC-Link Companion reads the selected register and transmits the read response packet to the BC-Link Mas-
ter. The Companion will ignore the read request if there is a CRC error; this will cause the Master state machine
to time-out and issue a BC_ERR Interrupt.
5. The Master state machine loads the Data Register, issues a BUSY Bit Clear interrupt and clears the BUSY bit to
‘0’.
6. Software, after either receiving the Bit Clear interrupt, or polling the BUSY bit until it is ‘0’, checks the BC_ERR
bit in the Status Register.
7. Software can now read the Data Register which contains the valid data if there was no BC Bus error.
8. If a Bus Error occurs, firmware must issue a soft reset by setting the RESET bit in the Status Register to ‘1’.
9. The read can re-tried once BUSY is cleared.
DS00001956D-page 420
 2015 - 2016 Microchip Technology Inc.