MEC1404 Datasheet, PDF (264/572 Pages) Microchip Technology – Keyboard and Embedded Controller Products for Notebook PC

MEC140X/1X
16.14.3 KEYBOARD STATUS READ REGISTER
This register is a read-only alias of the EC Keyboard Status Register.
Offset ^04h
Bits
Description
Type
7:6 UD2
R
User-defined data. Readable and writable by the EC when written
by the EC at its EC-only alias.
5 AUXOBF
R
Auxiliary Output Buffer Full. This bit is set to “1” whenever the EC
writes the EC AUX Data Register. This flag is reset to “0” when-
ever the EC writes the EC2Host Data Register.
4 UD1
R
User-defined data. Readable and writable by the EC when written
by the EC at its EC-only alias.
3 C/D
R
Command Data. This bit specifies whether the input data register
contains data or a command (“0” = data, “1” = command). During
a Host command write operation (when the Host writes the
HOST_EC Data / CMD Register at offset 04h), this bit is set to “1”.
During a Host data write operation (when the Host writes the
HOST_EC Data / CMD Register at offset 0h), this bit is set to “0”.
2 UD0
R
User-defined data. Readable and writable by the EC when written
by the EC at its EC-only alias.
Note: This bit is reset to ‘0’ when the LRESET# pin signal is
asserted.
1 IBF
R
Input Buffer Full. This bit is set to “1” whenever the Host writes data
or a command into the HOST_EC Data / CMD Register. When this
bit is set, the EC's IBF interrupt is asserted, if enabled. When the
EC reads the HOST2EC Data Register, this bit is automatically
reset and the interrupt is cleared.
Note:
This bit is not reset when VCC_PWRGD is asserted or
when the LPC interface powers down. To clear this bit,
firmware must read the HOST2EC Data Register in the
EC-Only address space.
0 OBF
R
Output Buffer Full. This bit is set when the EC writes a byte of Data
or AUX Data into the EC_HOST Data / AUX Data Register. When
the Host reads the HOST_EC Data / CMD Register, this bit is auto-
matically cleared by hardware and a OBF interrupt is generated.
Note:
This bit is not reset when VCC_PWRGD is asserted or
when the LPC interface powers down. To clear this bit,
firmware must read the HOST_EC Data / CMD Regis-
ter in the Runtime address space.
Default
0h
Reset
Event
nSYSR
ST
0h
nSYSR
ST
0h
nSYSR
ST
0h
nSYSR
ST
0h
nSYSR
ST and
PCI_RE
SET#
0h
nSYSR
ST
0h
nSYSR
ST
DS00001956D-page 264
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