MEC1404 Datasheet, PDF (313/572 Pages) Microchip Technology – Keyboard and Embedded Controller Products for Notebook PC

MEC140X/1X
TABLE 21-7:
SUBWEEK_
TICK
5
6
7
SUB-WEEK ALARM COUNTER CLOCK (CONTINUED)
Source
SPISR
Frequency
Minimum
Duration
Week Counter
n/a
bit 5
Week Counter
n/a
bit 7
Week Counter
n/a
bit 9
31.25 Hz
7.8125 Hz
1.95 Hz
32 sec
128 sec
512 sec
Maximum
Duration
272.5 min
18.17 hour
72.68 hour
Note 1: The Week Alarm Counter must not be modified by firmware if Sub-Week Alarm Counter is using the Week
Alarm Counter as its clock source (i.e., the SUBWEEK_TICK field is set to any of the values 4, 5, 6 or 7).
The Sub-Week Alarm Counter must be disabled before changing the Week Alarm Counter. For example,
the following sequence may be used:
1. Write 0h to the Sub-Week Alarm Counter Register (disabling the Sub-Week Counter)
2. Write the Week Alarm Counter Register
3. Write a new value to the Sub-Week Alarm Counter Register, restarting the Sub-Week Counter
21.9.1.3 15-bit Clock Divider
This counter is 15 bits wide. The clock for this counter is 32KHz_Clk, and as long as the RTC/Week Timer is enabled,
it is incremented at 32.768KHz rate. The Clock Divider automatically The Clock Divider generates a clock out of 1 Hz
when the counter wraps from 7FFFh to 0h.
By selecting one of the 15 bits of the counter, using the Sub-Second Programmable Interrupt Select Register, the Clock
Divider can be used either to generate a time base for the Sub-Week Alarm Counter or as an isochronous interrupt to
the EC, the SUB_SECOND interrupt.. See Table 21-10, "SPISR Encoding" for a list of available frequencies.
21.9.2 TIMER VALID STATUS
If power on reset occurs on the VBAT power rail while the main device power is off, the counters in the RTC/Week Alarm
are invalid. If firmware detects a POR on the VBAT power rail after a system boot, by checking the status bits in the
Power, Clocks and Resets registers, the RTC/Week Alarm block must be reinitialized.
21.9.3 APPLICATION NOTE: REGISTER TIMING
Register writes in the RTC/Week Alarm complete within two cycles of the 32KHz_Clk clock.The write completes even
if the main system clock is stopped before the two cycles of the 32K clock complete. Register reads complete in one
cycle of the internal bus clock.
All RTC/Week Alarm interrupts that are asserted within the same cycle of the 32KHz_Clk clock are synchronously
asserted to the EC.
21.9.4 APPLICATION NOTE: USE OF THE WEEK TIMER AS A 43-BIT COUNTER
The Week Timer cannot be directly used as a 42-bit counter that is incremented directly by the 32.768KHz clock domain.
The upper 28 bits (28-bit Week Alarm Counter) are incremented at a 1Hz rate and the lower 16 bits (15-bit Clock Divider)
are incremented at a 32.768KHz rate, but the increments are not performed in parallel. In particular, the upper 28 bits
are incremented when the lower 15 bits increment from 0 to 1, so as long as the Clock Divider Register is 0 the two
registers together, treated as a single value, have a smaller value then before the lower register rolled over from 7FFFh
to 0h.
The following code can be used to treat the two registers as a single large counter. This example extracts a 32-bit value
from the middle of the 43-bit counter:
dword TIME_STAMP(void)
{
AHB_dword wct_value;
AHB_dword cd_value1;
AHB_dword cd_value2;
dword irqEnableSave;
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