MEC1404 Datasheet, PDF (358/572 Pages) Microchip Technology – Keyboard and Embedded Controller Products for Notebook PC

MEC140X/1X
Offset ^10h
Bits
Description
Type
19 DISABLE_HARDWARE_FLOW_CONTROL
RW
This will Disable the Hardware Flow Control. When disabled, any
DMA Master device attempting to communicate to the DMA over the
DMA Flow Control Interface (Ports: dma_req, dma_term, and
dma_done) will be ignored.
This should be set before using the DMA channel in Firmware Flow
Control mode.
18 LOCK_CHANNEL
RW
This is used to lock the arbitration of the Channel Arbiter on this
channel once this channel is granted.
Once this is locked, it will remain on the arbiter until it has completed
it transfer (either the Transfer Aborted, Transfer Done or Transfer
Terminated conditions).
Note: This setting may starve other channels if the locked chan-
nel takes an excessive period of time to complete.
17 INCREMENT_DEVICE_ADDRESS
RW
This will enable an auto-increment to the DMA Channel Device
Address.
1: Increment the DMA Channel Device Address by DMA Channel
Control:Transfer Size after every Data Packet transfer
0: Do nothing
16 INCREMENT_MEMORY_ADDRESS
RW
This will enable an auto-increment to the DMA Channel Memory
Address.
1=Increment the DMA Channel Memory Address by DMA Channel
Control:Transfer Size after every Data Packet transfer
0=Do nothing
Note:
If this is not set, the DMA will never terminate the transfer
on its own. It will have to be terminated through the Hard-
ware Flow Control or through a DMA Channel Con-
trol:Transfer Abort.
15:9 HARDWARE_FLOW_CONTROL_DEVICE
RW
This is the device that is connected to this channel as its Hardware
Flow Control master.
The Flow Control Interface is a bus with each master concatenated
onto it. This selects which bus index of the concatenated Flow Con-
trol Interface bus is targeted towards this channel.
The Flow Control Interface Port list is dma_req, dma_term, and
dma_done.
8 TRANSFER_DIRECTION
RW
This determines the direction of the DMA Transfer.
1=Data Packet Read from Memory Start Address followed by Data
Packet Write to Device Address
0=Data Packet Read from Device Address followed by Data Packet
Write to Memory Start Address
7:6 Reserved
R
Default
0h
Reset
Event
DMA_R
ESET
0h
DMA_R
ESET
0h
DMA_R
ESET
0h
DMA_R
ESET
0h
DMA_R
ESET
0h
DMA_R
ESET
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DS00001956D-page 358
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