MEC1404 Datasheet, PDF (464/572 Pages) Microchip Technology – Keyboard and Embedded Controller Products for Notebook PC

MEC140X/1X
Conversions always start with the lowest-numbered enabled channel and proceed to the highest-numbered enabled
channel.
Note: If software repeatedly sets Start_Single to 1 at a rate faster than the Repeat Timer count down interval, the
conversion cycle defined by the ADC Repeat Register will not be executed.
38.10.1 REPEAT MODE
• Repeat Mode will start a conversion cycle of all ADC channels enabled by bits Rpt_En[7:0] in the ADC Repeat
Register. The conversion cycle will begin after a delay determined by Start_Delay[15:0] in the ADC Delay Regis-
ter.
• After all channels enabled by Rpt_En[7:0] are complete, Repeat_Done_Status will be set to 1. This status bit is
cleared when the next repeating conversion cycle begins to give a reflection of when the conversion is in prog-
ress.
• As long as Start_Repeat is 1 the ADC will repeatedly begin conversion cycles with a period defined by
Repeat_Delay[15:0].
• If the delay period expires and a conversion cycle is already in progress because Start_Single was written with a
1, the cycle in progress will complete, followed immediately by a conversion cycle using Rpt_En[7:0] to control the
channel conversions.
38.10.2 SINGLE MODE
• The Single Mode conversion cycle will begin without a delay. After all channels enabled by Single_En[7:0] are
complete, Single_Done_Status will be set to 1. When the next conversion cycle begins the bit is cleared.
• If Start_Single is written with a 1 while a conversion cycle is in progress because Start_Repeat is set, the conver-
sion cycle will complete, followed immediately by a conversion cycle using Single_En[7:0] to control the channel
conversions.
38.11 EC-Only Registers
The registers listed in the Table 38-3, "Analog to Digital Converter Register Summary" are for a single instance of the
Analog to Digital Converter block. The addresses of each register listed in this table are defined as a relative offset to
the host “Base Address” defined in Table 38-2, "Analog to Digital Converter Base Address Table".
TABLE 38-2: ANALOG TO DIGITAL CONVERTER BASE ADDRESS TABLE
Instance Name
ADC
Instance
Number
0
Host
EC
Address Space
32-bit internal
address space
Base Address
0000_7C00h
Note 38-1 The Base Address indicates where the first register can be accessed in a particular address space
for a block instance.
TABLE 38-3: ANALOG TO DIGITAL CONVERTER REGISTER SUMMARY
Offset
00h
04h
08h
0Ch
10h
Register Name (Mnemonic)
ADC Control Register
ADC Delay Register
ADC Status Register
ADC Single Register
ADC Repeat Register
DS00001956D-page 464
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