MEC1404 Datasheet, PDF (112/572 Pages) Microchip Technology – Keyboard and Embedded Controller Products for Notebook PC

MEC140X/1X
;
MOV
DX,CONFIG_PORT_BASE_ADDRESS
MOV
AL,60H
OUT
DX,AL ; Point to BASE ADDRESS REGISTER
MOV
DX,CONFIG_PORT_BASE_ADDRESS+1
MOV
AL,02H
OUT
DX,AL ; Update BASE ADDRESS REGISTER
;-----------------------------.
; DISABLE CONFIGURATION STATE
;-----------------------------'
MOV
DX,CONFIG_PORT_BASE_ADDRESS
MOV
AX,0AAH; Config Exit Key
OUT
DX,AL.
4.8.4 SERIAL IRQS
The device supports the serial interrupt scheme, which is adopted by several companies, to transmit interrupt informa-
tion to the system. The serial interrupt scheme adheres to the Serial IRQ Specification for PCI Systems Version 6.0..
4.8.4.1 Enabling SERIRQ Function
Each Serial IRQ channel defaults to disabled. To enable a Serial IRQ channel the host must program the Serial IRQ
Configuration Registers on page 118.
4.8.4.2 TIMING DIAGRAMS for SERIRQ CYCLE
LCLK = LCLK pin
SERIRQ = Serial IRQ pin
Start Frame timing with source sampled a low pulse on IRQ1
FIGURE 4-5:
SERIAL INTERRUPTS WAVEFORM “START FRAME”
LCLK
SERIRQ
Drive Source
SL
START FRAME
IRQ0 FRAME IRQ1 FRAME IRQ2 FRAME
or
H
H
RT SRT SRT SRT
START
IRQ1 ^{Host Controller}
None
IRQ1
None
H=Host Control
SL=Slave Control
R=Recovery
T=Turn-around
S=Sample
Start Frame pulse can be 4-8 clocks wide.
Stop Frame Timing with Host using 17 SERIRQ sampling period
DS00001956D-page 112
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