MEC1404 Datasheet, PDF (189/572 Pages) Microchip Technology – Keyboard and Embedded Controller Products for Notebook PC

MEC140X/1X
10.12.1 INTERRUPT SOURCE, ENABLE SET, ENABLE CLEAR, AND RESULT REGISTERS
All of the GIRQx Source, Enable, and Result registers have the same format. The following tables define the generic
format for each of these registers. The bit definitions are defined in Table 10-2, “Interrupt Source, Enable Set, Enable
Clear, and Result Bit Assignments,” on page 169.
TABLE 10-5: GIRQX SOURCE REGISTER FORMAT
Offset ^{See Table 10-4, "JTVIC Register Summary"}
Bits
Description
Type
31:9 Reserved
30:0 GIRQx Source Bit [30:0]
The GIRQx Source bits are R/WC sticky status bits indicating the
state of interrupt before the interrupt enable bit.
For GIRQx Bit Assignments see Table 10-2, “Interrupt Source,
Enable Set, Enable Clear, and Result Bit Assignments,” on page 169.
Unassigned bits are Reserved; Reads return 0.
R
R/WC
Default
-
0h
Reset
Event
-
nSYSR
ST
TABLE 10-6: GIRQX ENABLE SET REGISTER FORMAT
Offset ^{See Table 10-4, "JTVIC Register Summary"}
Bits
Description
Type
31:9 Reserved
30:0 GIRQx Enable Set [31:0]
Each GIRQx bit can be individually enabled to assert an interrupt
event.
0= Writing a zero has no effect.
1= Writing a one will enable respective GIRQx.
R
R/WS
Default
-
0h
Reset
Event
-
nSYSR
ST
Reading always returns the current value of the GIRQx ENABLE bit.
The state of the GIRQx ENABLE bit is determined by the correspond-
ing GIRQx Enable Set bit and the GIRQx Enable Clear bit. (0=dis-
abled, 1-enabled)
Note:
For GIRQx Bit Assignments see Table 10-2, “Interrupt
Source, Enable Set, Enable Clear, and Result Bit Assign-
ments,” on page 169. Unassigned bits are Reserved;
Reads return 0.
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