MEC1404 Datasheet, PDF (75/572 Pages) Microchip Technology – Keyboard and Embedded Controller Products for Notebook PC

MEC140X/1X
TABLE 3-9: DEFINITION OF RESET SIGNALS (CONTINUED)
Reset
Description
Source
nRESET_IN
nRESET_OUT
nSYSRST
LRESET#
eSPI_RESET#
eSPI_PLTRST#
PCI_RESET#
nSIO_RESET
WDT_RESET
EC_PROC_RES
ET#
External Pin that can generate the equivalent of
a VTR POR event. Asserting this signal will
cause the nSYSRST to be asserted, which
resets the majority of the chip.
Pin Interface
External Pin that can generate the equivalent of This signal is asserted low when the nSIO_RE-
a VCC POR or main reset event to other exter- SET is asserted low.
nal devices.
Internal VTR Reset signal. This signal is used
to reset VTR powered registers.
nSYSRST is asserted when VTRGD
is low, when a WDT_RESET event occurs, when
the nRESET_IN pin is asserted low, or when the
EJTAG.PrRST bit is asserted. It is only deas-
serted when VTRGD is high, nRESET_IN is
high, the EJTAG.PrRST bit is deasserted,.and
their is no WDT_RESET event active.
The EJTAG.PrRST bit is defined in the MIPS®
EJTAG Specification, DN: MD00047, Rev 5.06,
March 05, 2011.
System reset signal connected to the LPC LRE- Pin Interface
SET# pin (also referred to as PCI Reset).
System reset signal connected to the eSPI
eSPI_RESET# pin
Pin Interface
Platform Reset.
Generated by the eSPI Block when VCC_P-
WRGD is low, when eSPI_RESET# is low, by a
Virtual Wire, or by PC_Channel_Disable.
System reset signal
Generated by either the LPC LRESET# pin (also
referred to as PCI Reset) or the eSPI_PLTRST#
depending on the configuration of the Host_Re-
set_Select bit.
Performs a reset when VCC is turned off or
when the system host resets the LPC or eSPI
Host Interfaces.
nSIO_RESET is a signal that is asserted if
nSYSRST is low, VCC_PWRGD is low, or
PCI_RESET# is asserted low and may be deas-
serted when these three signals are all high. The
iRESET_OUT bit controls the deassertion of
nSIO_RESET.
A WDT_RESET event will also cause an
nSIO_RESET assertion.
Internal WDT Reset signal. This signal resets A WDT_RESET is asserted by a WDT Event.
VTR powered registers with the exception of This event is indicated by the WDT bit in the
the WDT Event Count register. Note that the Power-Fail and Reset Status Register
glitch protect circuits do not activate on a WDT
reset. WDT_RESETdoes not reset VBAT regis-
ters or logic.
Internal reset signal to reset the processor in
the EC Subsystem.
An EC_PROC_RESET# is a stretched version
of the nSYSRST. This reset asserts at the same
time that nSYSRST asserts and is held asserted
for 1ms after the nSYSRST deasserts.
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