MEC1404 Datasheet, PDF (192/572 Pages) Microchip Technology – Keyboard and Embedded Controller Products for Notebook PC

MEC140X/1X
TABLE 10-10: GIRQX [N+7:N] INTERRUPT PRIORITY REGISTER FORMAT (CONTINUED)
Offset ^-
Bits
9:8 GIRQX [N+2] Priority
00 = Priority Level 1
01 = Priority Level 3
10 = Priority Level 5
11 = Priority Level 7
7:6 Reserved
5:4 GIRQX [N+1] Priority
00 = Priority Level 1
01 = Priority Level 3
10 = Priority Level 5
11 = Priority Level 7
3:2 Reserved
1:0 GIRQX [N] Priority
00 = Priority Level 1
01 = Priority Level 3
10 = Priority Level 5
11 = Priority Level 7
Description
Type
R/W
Default
0h
R
-
R/W
0h
R
-
R/W
0h
Reset
Event
nSYSR
ST
-
nSYSR
ST
-
nSYSR
ST
10.12.4 JTVIC CONTROL REGISTERS
TABLE 10-11: JTVIC CONTROL REGISTER
Offset ^500h
Bits
Description
Type
31:9 Reserved
R
8 Vector Spacing
R/W
0 = 8 Bytes
1 = 512 Bytes
7:1 Reserved
R
0 Soft Reset
R/W
Soft Reset resets all flops in the JTVIC block except the interrupt
source bits and the soft reset bit itself.
0 = Not Reset - Normal Operation
1 = Reset
TABLE 10-12: INTERRUPT PENDING REGISTER
Offset ^504h
Bits
Description
Type
31:19 Reserved
R
18:0 GIRQ[26:8] Aggregated Group Interrupt Source Pending
R
This register shows the GIRQx pending interrupt sources. Each bit is
the OR’d result of the corresponding GIRQx Interrupt Source regis-
ter.
Default
-
00h
Reset
Event
-
nSYSR
ST
-
-
0h
nSYSR
ST
Default
-
0h
Reset
Event
-
nSYSR
ST
DS00001956D-page 192
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