MEC1404 Datasheet, PDF (129/572 Pages) Microchip Technology – Keyboard and Embedded Controller Products for Notebook PC

MEC140X/1X
4.11.4 EC CLOCK CONTROL REGISTER
Offset ^10h
Bits
Description
Type
31:3 RESERVED
2 Handshake
This bit controls throughput of LPC transactions.
When this bit is a ‘0’ the part supports a 33MHz PCI Clock. When
this bit is a ‘1’, the part supports a PCI Clock from 24MHz to 33MHz.
1:0 Clock_Control
RES
RES
R/W
This field controls when the host interface will permit the internal ring
oscillator to be shut down. The choices are as follows:
0h: The host interface will permit the internal clocks to be shut
down if the LPCPD# signal is asserted (sampled low)
1h: The host interface will permit the internal clocks to be shut down
if the CLKRUN# signals “CLOCK STOP” and there are no pending
serial interrupt request or DMA requests from devices associated
with the device. The CLKRUN# signals “CLOCK STOP” by
CLKRUN# being high for 5 LPCCLK’s after the raising edge of
CLKRUN#
2h: The host interface will permit the ring oscillator to be shut down
after the completion of every LPC transaction. This mode may cause
an increase in the time to respond to LPC transactions if the ring
oscillator is off when the LPC transaction is detected.
3h: The ring oscillator is not permitted to shut down as long as the
host interface is active
The bit in the LPC Activate Register should not be written ‘0’ to by
the Host over LPC. When the bit in the LPC Activate Register is 0,
the Host Interface will permit the ring oscillator to be shut down and
the Clock_Control Field is ignored. The Clock_Control Field only
effects the Host Interface when The bit in the LPC Activate Register
should not be written ‘0’ to by the Host over LPC. bit in the LPC Acti-
vate Register is 1.
Although the Host Interface can permit the internal oscillator to shut
down, it cannot turn the oscillator on in response to an LPC transac-
tion that occurs while the oscillator is off. In order to restart the oscil-
lator in order to complete an LPC transaction, EC firmware must
enable the LPC_WAKE interrupt. See the Application Note in Sec-
tion 10.11.3.1, "GIRQ16 and GIRQ22 Wake-Only Events" for details.
Default
-
1h
Reset
Event
-
nSYSRS
T
0h
nSYSRS
T
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DS00001956D-page 129