MEC1404 Datasheet, PDF (432/572 Pages) Microchip Technology – Keyboard and Embedded Controller Products for Notebook PC

MEC140X/1X
33.9 Description
33.9.1 BLOCK DIAGRAM
nSYSRST
48 MHz Ring Oscillator
Host Interface
Sleep Enable
24-bit Timer
FIFO
32-bit x 16
POWER
MGMT
BDP_INT
EC Interface
Clock Required
FIGURE 33-2:
Port 80 BIOS Debug Port BLOCK DIAGRAM
The Port 80 BIOS Debug Port consists of a 32-bit wide x 16 deep FIFO and a 24-bit free running timer. Host and EC
access to the Port 80 device is through a set of registers. The Host can write the FIFO via the Runtime Registers and
the EC can read the FIFO can control the device via the EC-Only Registers.
Writes to the Host Data Register are concatenated with the 24-bit timestamp and written to the FIFO. Reads of the
Host Data Register return zero. If writes to the Host Data Register overrun the FIFO, the oldest data are discarded and
the OVERRUN status bit in the Status Register is asserted.
Only the EC can read data from the FIFO, using the EC Data Register. The use of this data is determined by EC Firm-
ware alone.
33.10 Configuration Registers
The registers listed in the Configuration Register Summary table are for a single instance of the Port 80 BIOS Debug
Port. The addresses of each register listed in this table are defined as a relative offset to the host “Base Address”
defined in the Configuration Register Base Address Table.
FIGURE 33-3:
CONFIGURATION REGISTER BASE ADDRESS TABLE
Block Instance
Port 80 BIOS Debug
Port
Instance
Number
0
0
1
Host
LPC
EC
LPC
EC
Address Space
Configuration Port
32-bit internal
address space
Configuration Port
32-bit internal
address space
Base Address
INDEX = 00h
000F_5400h
INDEX = 00h
000F_5800h
Each Configuration register access through the Host Access Port is via its LDN and its Host Access Port Index. EC
access is a relative offset to the EC Base Address.
DS00001956D-page 432
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