MEC1404 Datasheet, PDF (296/572 Pages) Microchip Technology – Keyboard and Embedded Controller Products for Notebook PC

MEC140X/1X
18.9.3 TIMER STATUS REGISTER
Offset ^08h
Bits
Description
Type
31:0 Reserved
0 EVENT_INTERRUPT
This is the interrupt status that fires when the timer reaches its
limit. This may be level or a self clearing signal cycle pulse, based
on the AUTO_RESTART bit in the Timer Control Register. If the
timer is set to automatically restart, it will provide a pulse, otherwise
a level is provided.
R
R/WC
Default
-
0h
Reset
Event
-
Tim-
er_Re-
set
18.9.4 TIMER INT ENABLE REGISTER
Offset ^0Ch
Bits
Description
31:0 Reserved
0 EVENT_INTERRUPT_ENABLE
This is the interrupt enable for the status EVENT_INTERRUPT bit
in the Timer Status Register
Type
R
R/W
Default
-
0h
Reset
Event
-
Tim-
er_Re-
set
18.9.5 TIMER CONTROL REGISTER
Offset ^10h
Bits
Description
31:16 PRE_SCALE
This is used to divide down the system clock through clock enables
to lower the power consumption of the block and allow slow timers.
Updating this value during operation may result in erroneous clock
enable pulses until the clock divider restarts.
The number of clocks per clock enable pulse is (Value + 1); a setting
of 0 runs at the full clock speed, while a setting of 1 runs at half
speed.
15:8 Reserved
7 HALT
This is a halt bit. This will halt the timer as long as it is active. Once
the halt is inactive, the timer will start from where it left off.
Type
R/W
R
R/W
1=Timer is halted. It stops counting. The clock divider will also be
reset.
0=Timer runs normally
Default
0h
Reset
Event
Tim-
er_Reset
-
-
0h
Tim-
er_Reset
DS00001956D-page 296
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