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MEC1404 Datasheet, PDF (289/572 Pages) Microchip Technology – Keyboard and Embedded Controller Products for Notebook PC | |||
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MEC140X/1X
Offset 05h
Bits
Description
3 FRAME_ERROR
Framing Error. Bit 3 indicates that the received character did not
have a valid stop bit. Bit 3 is set to a logic â1â whenever the stop
bit following the last data bit or parity bit is detected as a zero bit
(Spacing level). This bit is reset to a logic â0â whenever the Line
Status Register is read. In the FIFO mode this error is associated
with the particular character in the FIFO it applies to. This error is
indicated when the associated character is at the top of the
FIFO. The Serial Port will try to resynchronize after a framing
error. To do this, it assumes that the framing error was due to the
next start bit, so it samples this 'start' bit twice and then takes in
the 'data'.
2 PARITY ERROR
Parity Error. Bit 2 indicates that the received data character does
not have the correct even or odd parity, as selected by the even
parity select bit. This bit is set to a logic â1â upon detection of a
parity error and is reset to a logic â0â whenever the Line Status
Register is read. In the FIFO mode this error is associated with
the particular character in the FIFO it applies to. This error is
indicated when the associated character is at the top of the
FIFO.
1 OVERRUN_ERROR
Overrun Error. Bit 1 indicates that data in the Receiver Buffer
Register was not read before the next character was transferred
into the register, thereby destroying the previous character. In
FIFO mode, an overrun error will occur only when the FIFO is full
and the next character has been completely received in the shift
register, the character in the shift register is overwritten but not
transferred to the FIFO. This bit is set to a logic â1â immediately
upon detection of an overrun condition, and reset whenever the
Line Status Register is read.
0 DATA_READY
Data Ready. It is set to a logic â1â whenever a complete incoming
character has been received and transferred into the Receiver
Buffer Register or the FIFO. Bit 0 is reset to a logic â0â by reading
all of the data in the Receive Buffer Register or the FIFO.
Type
R
R
R
R
Default
0h
Reset
Event
RESET
0h
RESET
0h
RESET
0h
RESET
ï£ 2015 - 2016 Microchip Technology Inc.
DS00001956D-page 289
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