MEC1404 Datasheet, PDF (249/572 Pages) Microchip Technology – Keyboard and Embedded Controller Products for Notebook PC

MEC140X/1X
15.11.2 POWER MANAGEMENT 1 STATUS 2 REGISTER
Offset ^01h
Bits
Description
Type
7 WAK_STS
This bit can be set or cleared by the EC. The Host writing a one to
this bit can also clear this bit.
6:4 Reserved
3 PWRBTNOR_STS
This bit can be set or cleared by the EC to simulate a Power button
override event status if the power is controlled by the EC. The Host
writing a one to this bit can also clear this bit. The EC must gener-
ate the associated hardware event under software control.
2 RTC_STS
This bit can be set or cleared by the EC to simulate a RTC status.
The Host writing a one to this bit can also clear this bit. The EC
must generate the associated SCI interrupt under software control.
1 SLPBTN_STS
This bit can be set or cleared by the EC to simulate a Sleep button
status if the sleep state is controlled by the EC. The Host writing a
one to this bit can also clear this bit. The EC must generate the
associated SCI interrupt under software control.
0 PWRBTN_STS
This bit can be set or cleared by the EC to simulate a Power button
status if the power is controlled by the EC. The Host writing a one
to this bit can also clear this bit. The EC must generate the associ-
ated SCI interrupt under software control.
R/WC
(See
Note:)
R
R/WC
(See
Note:)
R/WC
(See
Note:)
R/WC
(See
Note:)
R/WC
(See
Note:)
Default
00h
Reset
Event
nSYSR
ST
-
-
00h
nSYSR
ST
00h
nSYSR
ST
00h
nSYSR
ST
00h
nSYSR
ST
Note:
These bits are set/cleared by the EC directly i.e., writing ‘1’ sets the bit and writing ‘0’ clears it. These bits
can also be cleared by the Host software writing a one to this bit position and by nSYSRST. Writing a 0 by
the Host has no effect.
15.11.3 POWER MANAGEMENT 1 ENABLE 1 REGISTER
Offset ^02h
Bits
7:0 Reserved
Description
Type
R
Default
-
Reset
Event
-
 2015 - 2016 Microchip Technology Inc.
DS00001956D-page 249