MEC1404 Datasheet, PDF (208/572 Pages) Microchip Technology – Keyboard and Embedded Controller Products for Notebook PC

MEC140X/1X
12.9.7 EC DATA BYTE 2 REGISTER
Offset ^06h
Bits
Description
7:0 EC_DATA_BYTE_2
This is byte 2 of the 32-bit EC Data Register.
Use of the Data Byte registers to access EC memory is defined in
detail in Section 12.8.2, "EC Data Register".
12.9.8 EC DATA BYTE 3 REGISTER
Type
R/W
Default
0h
Reset
Event
nSYSR
ST
Offset ^07h
Bits
Description
Type
7:0 EC_DATA_BYTE_3
R/W
This is byte 3 (Most Significant Byte) of the 32-bit EC Data Register.
Use of the Data Byte registers to access EC memory is defined in
detail in Section 12.8.2, "EC Data Register".
Default
0h
Reset
Event
nSYSR
ST
12.9.9 INTERRUPT SOURCE LSB REGISTER
Offset ^08h
Bits
Description
Type
7:1 EC_SWI_LSB
EC Software Interrupt Least Significant Bits. These bits are soft-
ware interrupt bits that may be set by the EC to notify the host of an
event. The meaning of these bits is dependent on the firmware
implementation.
Each bit in this field is cleared when written with a ‘1b’. The ability
to clear the bit can be disabled by the EC if the corresponding bit in
the Host Clear Enable Register is set to ‘0b’. This may be used by
firmware for events that cannot be cleared while the event is still
active.
0 EC_WR
EC Mailbox Write. This bit is set when the EC-to-HOST Mailbox
Register has been written by the EC at offset 01h of the EC-Only
registers.
R/WC
R
Default
0h
Reset
Event
nSYSR
ST
0h
nSYSR
ST
DS00001956D-page 208
 2015 - 2016 Microchip Technology Inc.