MEC1404 Datasheet, PDF (452/572 Pages) Microchip Technology – Keyboard and Embedded Controller Products for Notebook PC

MEC140X/1X
TABLE 37-5: EC INTERRUPTS
Source
VCI_IN1
VCI_OVRD_IN
Description
This interrupt is routed to the Interrupt Controller It is only asserted when
both VBAT and VTR are powered. Edge detection and assertion level for
the interrupt are configured in the GPIO Pin Control Register for the GPIO
that shares the pin with VCI_IN# input. This interrupt is equivalent to the
GPIO interrupt for the GPIO that shares the pin, but appears on a differ-
ent register in the Interrupt Aggregator.
This interrupt is routed to the Interrupt Controller It is only asserted when
both VBAT and VTR are powered. Edge detection and assertion level for
the interrupt are configured in the GPIO Pin Control Register for the GPIO
that shares the pin with VCI_OVRD_IN input. This interrupt is equivalent
to the GPIO interrupt for the GPIO that shares the pin, but appears on a
different register in the Interrupt Aggregator.
37.7 Low Power Modes
The VBAT-powered Control Interface has no low-power modes. It runs continuously while the VBAT well is powered.
37.8 General Description
The VBAT-Powered Control Interface (VCI) is used to drive the VCI_OUT pin. The output pin can be controlled either
by VBAT-powered inputs, or by firmware when the VTR is active and the EC is powered and running. When the
VCI_OUT pin is controlled by hardware, either because VTR is inactive or because the VCI block is configured for hard-
ware control, the VCI_OUT pin can be asserted by a number of inputs:
• When either the VCI_IN0# pin or the VCI_IN1# is asserted. By default, the VCI_IN# pins are active low, but firm-
ware can switch each input individually to an active-high input. See Section 37.8.1, "Input Polarity".
• Wen the VCI_OVRD_IN pin is asserted. The VCI_OVRD_IN pin is always active high
• When the POWER_UP_EVENT from the RTC/Week Timer is asserted
Firmware can configure which of the hardware pin inputs contribute to the VCI_OUT output by setting the enable bits in
the VCI Input Enable Register. Even if the input pins are not configured to affect VCI_OUT, firmware can monitor their
current state through the status bits in the VCI Register. Firmware can also enable EC interrupts from the state of the
input pins.
Each of the VCI_IN# pins can be configured for additional properties.
• By default, each of the VCI_IN# pins have an input glitch filter. All glitch filters can be disabled by the FIL-
TERS_BYPASS bit in the VCI Register
• Assertions of each of the VCI_IN# pins can optionally be latched, so hardware can maintain the assertion of a
VCI_IN# even after the physical pin is de-asserted, or so that firmware can determine which of the VCI_IN# inputs
contributed to VCI_OUT assertion. See the Latch Enable Register and the Latch Resets Register.
• Rising edges and falling edges on the VCI_IN# pins are latched, so firmware can detect transitions on the
VCI_IN# pins even if the transitions occurred while EC power was not available. See Section 37.8.2, "Edge Event
Status".
When VTR power is present and the EC is operating, firmware can figure the VCI_OUT pin to operate as a general-
purpose output pin. The VCI_OUT pin is firmware-controlled when the FW_EXT bit in the VCI Register is ‘1’. When firm-
ware is controlling the output, the state of VCI_OUT is defined by the VCI_FW_CNTRL bit in the same register. When
VTR is not present (the VTRGD input is low), the VCI_OUT pin is also determined by the hardware circuit.
DS00001956D-page 452
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