MEC1404 Datasheet, PDF (135/572 Pages) Microchip Technology – Keyboard and Embedded Controller Products for Notebook PC

MEC140X/1X
6.8 Interrupts
This section defines the Interrupt Sources generated from this block.
Source
Description
QMSPI_INT
Interrupt generated by the Quad SPI Master Controller. Events that may
cause the interrupt to be asserted are stored in the QMSPI Status
Register.
6.9 Low Power Modes
The Quad SPI Master Controller is always in its lowest power state unless a transaction is in process. A transaction is
in process between the time the START bit is written with a ‘1’ and the TRANSFER_DONE bit is set by hardware to ‘1’.
If the QMSPI SLEEP_ENABLE input is asserted, writes to the START bit are ignored and the Quad SPI Master Control-
ler will remain in its lowest power state.
6.10 Description
• Support for multiple SPI pin configurations
- Single wire half duplex
- Two wire full duplex
- Two wire double data rate
- Four wire quad data rate
• Separate FIFO buffers for Receive and Transmit
- 8 byte FIFO depth in each FIFO
- Each FIFO can be 1 byte, 2 bytes or 4 bytes wide
• Support for all four SPI clock formats
• Programmable SPI Clock generator, with clock polarity and phase controls
• Separate DMA support for Receive and Transmit data transfers
• Configurable interrupts, for errors, individual bytes, or entire transactions
• Descriptor Mode, in which a set of five descriptor registers can configure the controller to autonomously perform
multi-phase SPI data transfers
• Capable of wire speed transfers in all SPI modes and all configurable SPI clock rates (internal bus contention may
cause clock stretching)
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DS00001956D-page 135