MEC1404 Datasheet, PDF (136/572 Pages) Microchip Technology – Keyboard and Embedded Controller Products for Notebook PC

MEC140X/1X
FIGURE 6-2:
QUAD MASTER SPI BLOCK DIAGRAM
Internal
Data Bus
State
Machine
SPI_IO0
Register _Shift
SPI_IO1
SPI_IO2
SPI_IO3
Clock
Generator
SPI_CK
SPI_CS#
Descriptor
Registers
6.10.1 SPI CONFIGURATIONS MODES
• Half Duplex. All SPI data transfers take place on a single wire, SPI_IO0
• Full Duplex. This is the legacy SPI configuration, where all SPI data is transfered one bit at a time and data from
the SPI Master to the SPI Slave takes place on SPI_MOSI (SPI_IO0) and at the same time data from the SPI
Slave to the SPI Master takes place on SPI_MISO (SPI_IO1)
• Dual Data Rate. Data transfers between the SPI Master and the SPI Slave take place two bits at a time, using
SPI_IO0 and SPI_IO1
• Quad Data Rate. Data transfers between the SPI Master and the SPI Slave take place four bits at a time, using all
four SPI data wires, SPI_IO0, SPI_IO1, SPI_IO2 and SPI_IO3
6.10.2 SPI CONTROLLER MODES
• Manual. In this mode, firmware control all SPI data transfers byte at a time
• DMA. Firmware configures the SPI Master controller for characteristics like data width but the transfer of data
between the FIFO buffers in the SPI controller and memory is controlled by the DMA controller. DMA transfers can
take place from the Slave to the Master, from the Master to the Slave, or in both directions simultaneously
• Descriptor. Descriptor Mode extends the SPI Controller so that firmware can configure a multi-phase SPI transfer,
in which each phase may have a different SPI bus width, a different direction, and a different length. For example,
firmware can configure the controller so that a read from an advanced SPI Flash, which consists of a command
DS00001956D-page 136
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