MEC1404 Datasheet, PDF (161/572 Pages) Microchip Technology – Keyboard and Embedded Controller Products for Notebook PC

8.5.3 RESETS
MEC140X/1X
Name
EC_PROC_RESET#
DESCRIPTION
The embedded controller is reset by EC_PROC_RESET#.
8.6 Interrupts
The embedded controller does not generate any interrupts.
Note: The embedded controller is equipped with an Interrupt Interface to respond to interrupts. See Section 8.4.6,
"Interrupt Interface," on page 160.
8.7 Exceptions
Exceptions are synchronous to instructions, are not maskable, and have higher priority than interrupts.
Name
Reset_Exception
Debug_Exception
NMI
Description
The Reset_Exception is asserted when either an SI_RESET (i.e., Soft
Reset) or a SI_ColdReset (i.e., POR) is asserted. Events that can cause
a SI_RESET are a Soft Reset initiated by firmware or a WDT Event.
The Debug_Exception is asserted for an EJTAG command.
None - There are no NMI’s implemented in this device.
8.8 Low Power Modes
The embedded controller may put itself and the chip into lower power states by configuring the chip’s Sleep logic imple-
mented in the chip’s Power, Clocks, and Reset (PCR) circuitry and then executing the WAIT instruction.
The core provides two mechanisms for system-level, low-power support: Register-controlled power management and
Instruction-controlled power management
8.8.1 REGISTER-CONTROLLED POWER MANAGEMENT
Register-Controlled Power Management is not supported.
8.8.2 INSTRUCTION-CONTROLLED POWER MANAGEMENT
In instruction-controlled power-down mode execution of the WAIT instruction is used to invoke low-power mode and put
the chip into sleep mode. It stays in sleep mode until an interrupt or restart occurs. Power consumption is reduced during
sleep mode since the pipeline ceases to change state, and the RAMs are disabled. More power reduction is achieved
when clock gating option is used, whereby all non-essential clocks are switched off. The chip’s Power, Clocks, and
Reset (PCR) circuitry may be enabled to gate the clocks externally to the core when the embedded controller enters the
sleep state.
8.9 Description
The block diagram shown in FIGURE 8-1: MIPS32 M14K Embedded Controller I/O Block Diagram on page 158 illus-
trates the IP configuration selected. This EC design includes the Fixed/Required M14K features, such as the Decode,
Execution Unit, etc that are shaded light gray. The EC design has also opted to include the microMIPs instruction set
and Debug capabilities. All other optional features have not been implemented.
The following sections define
used in combination with the
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Manual, listed in the Section 8.2, "References," on page 157.
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DS00001956D-page 161