MEC1404 Datasheet, PDF (157/572 Pages) Microchip Technology – Keyboard and Embedded Controller Products for Notebook PC

MEC140X/1X
8.0 MIPS32 M14K EMBEDDED CONTROLLER
8.1 Features
• A Modified 5-stage pipelined Harvard Architecture with a Closely-Coupled Data Memory and Instruction Memory
interfaces
• Single Cycle 32-bit instruction set
• microMIPS-Compatible Instruction Set (default)
- microMIPS supports all MIPS32 instructions (except branch-likely instructions)
- Stack pointer implicit in instruction
- MIPS32 assembly and ABI (Application Binary Interface) compatible.
• External Interrupt Controller (EIC) mode.
- Programmable exception vector base
- Atomic interrupt enable/disable
- Bit field manipulation instructions
• Simple Fixed Mapping Translation (FMT) mechanism
• Multiply/Divide Unit (high-performance configuration)
- Maximum issue rate of one 32x16 multiply per clock via on-chip 32x16 hardware multiplier array.
- Maximum issue rate of one 32x32 multiply every other clock
- Early-in iterative divide. Minimum 11 and maximum 34 clock latency (dividend (rs) sign extension-dependent)
• Power Control
- Programmable Clock Rates: 48 MHz, 24 MHz, 3 MHz, and 1 MHz
- Sleep mode: Minimum frequency: 0 MHz
- Power-down mode (triggered by WAIT instruction)
- Clocks are gated in Low Power Modes
• EJTAG Debug Mechanism
- CPU control with start, stop, and single-stepping
- Virtual instruction and data address/value breakpoints
- Hardware breakpoint supports both address match and address range triggering.
- Simple hardware breakpoints on virtual addresses: 4I/2D breakpoints
- PC/Address Sampling function
- Support EJTAG (IEEE 1149.1)
- Supported by MPLAB REAL ICE tools
8.2 References
1. MIPS32^ M14K™ Processor Core Software User’s Manual, Document Number: MD00668, Revision 02.03, April
30, 2012
2. MIPS32^ M14K™ Processor Core Data Sheet, Document Number MD00666, Revision 2.03, April 30, 2012
3. MIPS32^ M14K™ Architecture for Programmers Volume I-B: Introduction to the microMIPS32™ Architecture,
Document Number MD00741, Revision 3.02, March 21, 2011
4. MIPS32^ M14K™ Architecture for Programmers Volume II-B: The microMIPS32™ Instruction Set, Document
Number MD00582, Revision 3.05, April 04, 2011
5. MIPS^ EJTAG Specification, Document Number MD00047, Revision 5.06, March 05, 2011
Note: Resources for the MIPS32^® M4K™ Processor Core are available at: www.imgtec.com.
8.3 Terminology
There is no terminology defined for this chapter.
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