MEC1404 Datasheet, PDF (301/572 Pages) Microchip Technology – Keyboard and Embedded Controller Products for Notebook PC

MEC140X/1X
Note: The logic clocked by the system clock is considered to be in the idle state when the host is not accessing
the register interface.
TABLE 19-5: RTOS Timer - SYSTEM CLOCK POWER STATES
POWER STATE
Idle
Block
Enable
BIT
x
Sleep
Enable
x
Operating
x
x
Clock
Required
0
1
DESCRIPTION
Block is idle and operating in its lowest
power consumption state. The 48 MHz
Ring Oscillator is not used in this state.
The block automatically enters this state
anytime it is not performing a function
requiring this clock source (e.g.,
Register accesses).
Block is not idle. This block will assert
Clock Required signal only during
register access and when it needs to
generate interrupt. The sleep_en signal
has no effect on this clock requirement.
Note: The RTOS Timer Registers are readable and writable in all defined Power States.
19.7.2 WAKING FROM LOW POWER STATES
The chip Power, Clocks, and Resets logic is responsible for monitoring wake events that turn on 48 MHz Ring Oscillator.
The RTOS_TIMER interrupt event is a wake-capable event that may be used to turn on 48 MHz Ring Oscillator.
19.8 Description
The RTOS Timer is a very basic timer with simple down counter functionality with auto-reload and halt features. The
timer counts with Timer Clock when the timer is programmed with pre-load value.
The counter can be configured as one-shot timer by not setting the Auto Reload bit. The timer will load the value of the
pre-load register and start to count down when the Timer Start bit is asserted by the firmware. The timer will generate
interrupt when the counter transitions from count = 1 to count = 0 as defined in the Interrupt Generation section.
If the timer is needed again with same pre-load value, firmware has to only set the Timer Start bit. This will restart the
timer again.
The counter can also be programmed as continuous running mode by enabling the Auto Reload bit. In this mode counter
reloads itself every time timer equals 0. The timer also generates interrupt as defined in the interrupt section.
If the RTOS Timer Pre-Load register is written when the counter is counting, the new preload value will take effect only
when the counter reaches 0 if the auto-reload bit has been set.
If the RTOS Timer Pre-Load register is programmed with 32’h0 while the Timer is counting, the Timer will continue to
count until it counts to 0. Then the Timer Start bit will be cleared. If the Timer Start bit is written when the RTOS Timer
Pre-Load register is 0, the Timer Start bit will be self-cleared.
19.8.1 EXTERNAL HARDWARE HALT
The Halt signal is an input signal to the block. This signal when asserted (high) and enabled in the Timer Control Reg-
ister will halt the counter. When this signal is de-asserted (low), the timer will continue to count.
19.8.2 FIRMWARE HALT
The Timer can also be halted by setting Firmware Timer Halt bit in the Timer Control Register.
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