MEC1404 Datasheet, PDF (269/572 Pages) Microchip Technology – Keyboard and Embedded Controller Products for Notebook PC

MEC140X/1X
16.16 Legacy Port92/GATEA20 Configuration Registers
The registers listed in the Configuration Register Summary table are for a single instance of the Legacy
Port92/GATEA20 logic. The addresses of each register listed in this table are defined as a relative offset to the host
“Base Address” defined in the Configuration Register Base Address Table.
TABLE 16-11: CONFIGURATION BASE ADDRESS TABLE
Block Instance
Port92-Legacy
Instance
Number
0
Logical
Device
Number
1
Host
LPC
EC
Address Space
Configuration Port
32-bit internal
address space
Base Address
INDEX = 00h
000F_1800h
Each Configuration register access through the Host Access Port is via its LDN and its Host Access Port Index. EC
access is a relative offset to the EC Base Address.
TABLE 16-12: CONFIGURATION REGISTER SUMMARY
Offset
30h
Register Name (Mnemonic)
Port 92 Enable Register
16.16.1 PORT 92 ENABLE REGISTER
Offset ^30h
Bits
Description
Type
7:1 Reserved
R
0 P92_EN
R/W
When this bit is ‘1’, the Port92h Register is enabled. When this bit
is ‘0’, the Port92h Register is disabled, and Host writes to LPC
address 92h are ignored.
Default
-
0h
Reset
Event
-
VCC_P-
WRGD
and
nSYSR
ST
16.17 Legacy Port92/GATEA20 Runtime Registers
The registers listed in the Runtime Register Summary table are for a single instance of the Legacy Port92/GATEA20
logic. The addresses of each register listed in this table are defined as a relative offset to the host “Base Address”
defined in the Runtime Register Base Address Table.
 2015 - 2016 Microchip Technology Inc.
DS00001956D-page 269