MEC1404 Datasheet, PDF (351/572 Pages) Microchip Technology – Keyboard and Embedded Controller Products for Notebook PC

MEC140X/1X
Source
Description
DMA0
DMA1
DMA2
DMA3
DMA4
DMA5
DMA6
Direct Memory Access Channel 0
This signal is generated by the STATUS_DONE bit.
Direct Memory Access Channel 1
This signal is generated by the STATUS_DONE bit.
Direct Memory Access Channel 2
This signal is generated by the STATUS_DONE bit.
Direct Memory Access Channel 3
This signal is generated by the STATUS_DONE bit.
Direct Memory Access Channel 4
This signal is generated by the STATUS_DONE bit.
Direct Memory Access Channel 5
This signal is generated by the STATUS_DONE bit.
Direct Memory Access Channel 6
This signal is generated by the STATUS_DONE bit.
24.8 Low Power Modes
The Internal DMA Controller may be put into a low power state by the chip’s Power, Clocks, and Reset (PCR) circuitry.
When the block is commanded to go to sleep it will place the DMA block into sleep mode only after all transactions on
the DMA have been completed. For Firmware Flow Controlled transactions, the DMA will wait until it hits its terminal
count and clears the Go control bit. For Hardware Flow Control, the DMA will go to sleep after either the terminal count
is hit, or the Master device flags the terminate signal.
24.9 Description
The MEC140X/1X features a multi-channel DMA controller. The DMA controller can autonomously move data from/to
any DMA capable master device to/from any populated memory location. This mechanism allows hardware IP blocks
to transfer large amounts of data into or out of memory without EC intervention.
The DMA has the following characteristics:
• Data is only moved 1 Data Packet at a time
• Data only moves between devices on the accessible via the internal 32-bit address space
• Each DMA Channel may be configured to communicate with any DMA capable device on the 32-bit internal
address space. Each device has been assigned a device number. See Section 24.5.3, "DMA Interface," on
page 349.
The controller will accesses SRAM buffers only with incrementing addresses (that is, it cannot start at the top of a buffer,
nor does it handle circular buffers automatically). The controller does not handle chaining (that is, automatically starting
a new DMA transfer when one finishes).
A DMA Channel can optionally generate a CRC-32 on the data transfered by the Channel.
24.9.1 CONFIGURATION
The DMA Controller is enabled via the ACTIVATE bit in DMA Main Control Register register.
Each DMA Channel must also be individually enabled via the CHANNEL_ACTIVATE bit in the DMA Channel N Activate
Register to be operational.
Before starting a DMA transaction on a DMA Channel the host must assign a DMA Master to the channel via bits[15:9]
HARDWARE_FLOW_CONTROL_DEVICE. The host must not configure two different channels to the same DMA Mas-
ter at the same time.
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DS00001956D-page 351