MEC1404 Datasheet, PDF (276/572 Pages) Microchip Technology – Keyboard and Embedded Controller Products for Notebook PC

MEC140X/1X
17.8 Low Power Modes
The UART may be put into a low power state by the chip’s Power, Clocks, and Reset (PCR) circuitry.
17.9 Description
The UART is compatible with the 16450, the 16450 ACE registers and the 16C550A. The UART performs serial-to-par-
allel conversions on received characters and parallel-to-serial conversions on transmit characters. Two sets of baud
rates are provided. When the 1.8432 MHz source clock is selected, standard baud rates from 50 to 115.2K are available.
When the source clock is 32.26 MHz, baud rates from 126K to 2,016K are available. The character options are program-
mable for 1 start; 1, 1.5 or 2 stop bits; even, odd, sticky or no parity; and prioritized interrupts. The UART contains a
programmable baud rate generator that is capable of dividing the input clock signal by 1 to 65535. The UART is also
capable of supporting the MIDI data rate. Refer to the Configuration Registers for information on disabling, powering
down and changing the base address of the UART. The UART interrupt is enabled by programming OUT2 of the UART
to logic “1.” Because OUT2 is logic “0,” it disables the UART's interrupt. The UART is accessible by both the Host and
the EC.
17.9.1 PROGRAMMABLE BAUD RATE
The Serial Port contains a programmable Baud Rate Generator that is capable of dividing the internal clock source by
any divisor from 1 to 65535. The clock source is either the 1.8432MHz_Clk clock source or the 24MHz_Clk clock source.
The output frequency of the Baud Rate Generator is 16x the Baud rate. Two eight bit latches store the divisor in 16 bit
binary format. These Divisor Latches must be loaded during initialization in order to ensure desired operation of the
Baud Rate Generator. Upon loading either of the Divisor Latches, a 16 bit Baud counter is immediately loaded. This
prevents long counts on initial load. If a 0 is loaded into the BRG registers, the output divides the clock by the number
3. If a 1 is loaded, the output is the inverse of the input oscillator. If a two is loaded, the output is a divide by 2 signal with
a 50% duty cycle. If a 3 or greater is loaded, the output is low for 2 bits and high for the remainder of the count.
The following tables show possible baud rates.
TABLE 17-2: UART BAUD RATES USING CLOCK SOURCE 1.8432MHz_Clk
Desired Baud Rate
50
75
110
134.5
150
300
600
1200
1800
2000
2400
3600
4800
7200
9600
BAUD_CLOCK_SEL
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Divisor Used to Generate
16X Clock
2304
1536
1047
857
768
384
192
96
64
58
48
32
24
16
12
DS00001956D-page 276
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