MEC1404 Datasheet, PDF (354/572 Pages) Microchip Technology – Keyboard and Embedded Controller Products for Notebook PC

MEC140X/1X
24.11 DMA Channel Registers
The addresses of each register listed in these tables are defined as a relative offset to the “Base Address” defined in
the DMA Channel N Register Base Address Table. The Base Address indicates where the first register can be accessed
in a particular bank of registers.
TABLE 24-5: DMA CHANNEL N REGISTER BASE ADDRESS TABLE
Instance Name
DMA Controller
DMA Controller
DMA Controller
DMA Controller
DMA Controller
DMA Controller
DMA Controller
Channel
Number
(N)
0
(Note 1)
1
2
3
4
5
6
Host
EC
EC
EC
EC
EC
EC
EC
Address Space
32-bit internal
address space
32-bit internal
address space
32-bit internal
address space
32-bit internal
address space
32-bit internal
address space
32-bit internal
address space
32-bit internal
address space
Base Address
0000_2440h
0000_2480h
0000_24C0h
0000_2500h
0000_2540h
0000_2580h
0000_25C0h
Note 1: Only DMA Channel 0 has CRC-32 generation support, which can be used with the Quad SPI Master Con-
troller or for Memory-to-Memory DMA transfers.
TABLE 24-6: DMA CHANNEL N REGISTER SUMMARY
Offset
00h
04h
08h
0Ch
10h
14h
18h
1Ch
20h
(Note 3)
Register Name (Mnemonic)
(Note 2)
DMA Channel N Activate Register
DMA Channel N Memory Start Address Register
DMA Channel N Memory End Address Register
DMA Channel N Device Address Register
DMA Channel N Control Register
DMA Channel N Interrupt Status Register
DMA Channel N Interrupt Enable Register
Test
DMA Channel N CRC Enable Register
DS00001956D-page 354
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