MEC1404 Datasheet, PDF (217/572 Pages) Microchip Technology – Keyboard and Embedded Controller Products for Notebook PC

MEC140X/1X
13.7 Power, Clocks and Reset
This section defines the Power, Clock, and Reset parameters of the block.
13.7.1 POWER DOMAINS
VTR
Name
13.7.2 CLOCK INPUTS
Description
The logic and registers implemented in this block are powered by this
power well.
Name
48 MHz Ring Oscillator
13.7.3 RESETS
Description
This is the clock source for Mailbox logic.
nSYSRST
Name
VCC_PWRGD
13.8 Interrupts
Description
This signal resets all the registers and logic in this block to their default
state.
This signal is asserted when the main power rail is asserted. The Host
Access Port is reset when this signal is de-asserted.
Source
MBX_Host_SIRQ
MBX_Host_SMI
MBX
MBX_DATA
Source
Description
This interrupt source for the SIRQ logic is generated when the EC_WR
bit is ‘1’ and enabled by the EC_WR_EN bit.
This interrupt source for the SIRQ logic is generated when any of the
EC_SWI bits are asserted and the corresponding EC_SWI_EN bit are
asserted as well. This event is also asserted if the EC_WR/EC_WR_EN
event occurs as well.
This bit is also routed to the nSMI pin.
Description
Interrupt generated by the host writing the HOST-to-EC Mailbox register.
Interrupt generated by the host writing the MBX_DATA register.
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DS00001956D-page 217