MEC1404 Datasheet, PDF (306/572 Pages) Microchip Technology – Keyboard and Embedded Controller Products for Notebook PC

MEC140X/1X
20.6 Host Interface
The registers defined for the Hibernation Timer are accessible by the various hosts as indicated in Section 20.10, "EC-
Only Registers".
20.7 Power, Clocks and Reset
This section defines the Power, Clock, and Reset parameters of the block.
20.7.1 POWER DOMAINS
VTR
Name
20.7.2 CLOCK INPUTS
Description
The timer control logic and registers are all implemented on this single
power domain.
5Hz_Clk
Name
20.7.3 RESETS
Description
This is the clock source to the timer logic. The Pre-scaler may be used
to adjust the minimum resolution per bit of the counter.
if the main oscillator is stopped then an external 32.768kHz clock source
must be active for the Hibernation Timer to continue to operate.
Name
Description
nSYSRST
This reset signal, which is an input to this block, resets all the logic and
registers to their initial default state.
20.8 Interrupts
This section defines the interrupt Interface signals routed to the chip interrupt aggregator.
Each instance of the Hibernation Timer in the MEC140X/1X can be used to generate interrupts and wake-up events
when the timer decrements to zero.
TABLE 20-1: INTERRUPT INTERFACE SIGNAL DESCRIPTION TABLE
Name
HTIMER
Direction
Output
Description
Signal indicating that the timer is enabled and decrements to 0.
This signal is used to generate an Hibernation Timer interrupt
event.
20.9 Low Power Modes
The Hibernation Timer may be put into a low power state by the chip Power, Clocks, and Reset (PCR) circuitry.
The timer operates off of the 5Hz_Clk, and therefore will operate normally when 48 MHz Ring Oscillator is stopped.
DS00001956D-page 306
 2015 - 2016 Microchip Technology Inc.