MEC1404 Datasheet, PDF (483/572 Pages) Microchip Technology – Keyboard and Embedded Controller Products for Notebook PC

MEC140X/1X
Offset ^{01h (continued)}
Bits
Description
Type
7:0 Command 0x08: DeviceID
R/W
Bit [31:16] Device ID
Bit [15:8] Sub ID
Bit [7:0] Revision ID
The Device ID, Sub Id, and Revision ID are a reflection of the value
in the same registers defined in Table 7-2, “Chip-Level (Global)
Control/Configuration Registers,” on page 154 starting at offset
1Ch.
Note: This command only executes while Configuration
Ready (CFGRDY) is set.
Command 0x09: SetBootIntoUserCode
Sets the MTAP Boot into User Code status bit.
Note: This function only works while the Boot Ready status is
set.
Command 0x0A: ClrBootIntoUserCode
Clears the MTAP Boot into User Code status bit.
Note: This function only works while the Boot Ready status is
set.
Command 0xD1: AssertDeviceReset
Causes a VTR POR. Test functions remain uneffected.
Note: DEVRST, Device Reset Status, reflects the state of the
reset event.
Command 0xD0: DeassertDeviceReset
Clears the AssertDeviceReset.
Default
0h
Reset
Event
JTAG_
RST#
41.4.4.7 BYPASS <0x1F>
Standard JTAG BYPASS. TDI connected to TDO via a 1-bit Bypass register.
41.4.5 TEST MODE ENTRY
The MCLR pin is used as MCLR for the ICSP interface. The device pulls this signal high internally. The debug connector
must drive this signal correctly to enter ICSP modes.
41.4.5.1 Entry Sequence
To Enter ICSP:
1. Drive MCLR# High.
2. Drive ICSP_CLK and ICSP_DAT Low.
3. Drive MCLR# Low.
4. Send down 32 ICSP Clocks with the Test Mode Entry Code.
5. Drive MCLR# High
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DS00001956D-page 483