MEC1404 Datasheet, PDF (127/572 Pages) Microchip Technology – Keyboard and Embedded Controller Products for Notebook PC

MEC140X/1X
TABLE 4-19: EC-ONLY REGISTER SUMMARY (CONTINUED)
Offset
2Ch
30h
40h
FCh
Register Name
Reserved
LPC BAR Init Register
Device Memory BAR Inhibit Register
SRAM Memory Host Configuration Register
Note 4-1 Some Test registers are read/write registers. Modifying these registers may have unwanted results.
4.11.1 LPC BUS MONITOR REGISTER
Offset ^04h
Bits
31:2 RESERVED
1 TEST
Description
Type
RES
R
0 LPCPD_STATUS
R
This bit reflects the state of the LPCPD# input pin. The
LPCPD_STATUS bit is the inverse of the LPCPD# pin (see Section
4.8.1.3, "LPC Clock Run and LPC Power Down Behavior," on
page 104).
When the LPCPD_STATUS bit is ‘0b’, the LPCPD# input pin is
deasserted (that is, the pin has the value ‘1b’). When the
LPCPD_STATUS bit is ‘1b’, the LPCPD# input pin is asserted (that
is, the pin has the value ‘0b’).
Default
-
0h
0h
Reset
Event
-
nSYSR
ST
nSYSR
ST
4.11.2 HOST BUS ERROR REGISTER
Offset ^08h
Bits
Description
Type
31:8 ErrorAddress[23:16]
This 24-bit field captures the 24-bit internal address of every LPC
transaction whenever the bit LPC_INTERNAL_ERR in this register
is 0. When LPC_INTERNAL_ERR is 1 this register is not updated
but retains its previous value. When bus errors occur this field
saves the address of the first address that caused an error.
5 DMA_ERR
This bit is set to 1 whenever EN_INTERNAL_ERR is 1 and an LPC
DMA access causes an internal bus error. Once set, it remains set
until cleared by being written with a 1.
R
R/WC
Default
0h
Reset
Event
nSYSR
ST
0h
nSYSR
ST
 2015 - 2016 Microchip Technology Inc.
DS00001956D-page 127