MEC1404 Datasheet, PDF (74/572 Pages) Microchip Technology – Keyboard and Embedded Controller Products for Notebook PC

MEC140X/1X
3.6 Resets
FIGURE 3-2:
RESETS DIAGRAM (MEC140X/1X)
VTR_RESET#
WDT
RESET_IN#
nSYSRST
iRESET_OUT
VCC_PWRGD
eSPI_RESET#
VTR
eSPI Controller
PC_Channel_Disable
LRESET#
PCI_RESET#
Host_Reset_Select
eSPI_PLTRST#
PLTRST# Virtual Wire
PLTRST_SRC
Note: PC_Channel_Disable, PLTRST#
Virtual Wire, and PLTRST_SRC are defined
in eSPI Controller Specification.
nSIO_RESET
nRESET_OUT
TABLE 3-9:
Reset
VBAT_POR
VTR_RESET#
DEFINITION OF RESET SIGNALS
Description
Internal VBAT Reset signal. This signal is used
to reset VBAT powered registers.
VTR_RESET# is a Power-On-Reset.
Source
VBAT_POR is a pulse that is asserted at the ris-
ing edge of VTRGD if the VBAT voltage is below
a nominal 1.25V. VBAT_POR is also asserted as
a level if, while VTRGD is not asserted (‘0’), the
coin cell is replaced with a new cell that delivers
at least a nominal 1.25V. In this latter case
VBAT_POR is de-asserted when VTRGD is
asserted. No action is taken if the coin cell is
replaced, or if the VBAT voltage falls below 1.25
V nominal, while VTRGD is asserted.
VTR_RESET# is deasserted at the rising edge
of VTRGD and is asserted only when VTRGD is
low.
DS00001956D-page 74
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