MEC1404 Datasheet, PDF (194/572 Pages) Microchip Technology – Keyboard and Embedded Controller Products for Notebook PC

MEC140X/1X
11.0 WATCHDOG TIMER (WDT)
11.1 Introduction
The function of the Watchdog Timer is to provide a mechanism to detect if the internal embedded controller has failed.
When enabled, the Watchdog Timer (WDT) circuit will generate a WDT Event if the user program fails to reload the WDT
within a specified length of time known as the WDT Interval.
11.2 References
No references have been cited for this chapter.
11.3 Terminology
There is no terminology defined for this chapter.
11.4 Interface
This block is designed to be accessed internally via a registered host interface or externally via the signal interface.
11.4.1 SIGNAL DESCRIPTION
TABLE 11-1: SIGNAL DESCRIPTION TABLE
Name
WDT_Stall[2:0]
Direction
Input
Description
External 3-bit wide bus used to stall the WDT. Each of these sig-
nals may prevent the WDT from generating false WDT Events.
TABLE 11-2: MEC140X/1X WDT_STALL CONNECTIONS
Signal Name
WDT_Stall[0]
WDT_Stall[1]
WDT_Stall[2]
Control Signals
Hibernation Timer
Week Timer Active
ICSP Active
Description
If enabled via the WDT_STALL_EN[0], the WDT will be stalled when
the Hibernation Timer is counting.
If enabled via the WDT_STALL_EN[1], the WDT will be stalled if the
Week Timer is counting.
If enabled via the WDT_STALL_EN[2], the WDT will be stalled if
there is activity on the ICSP ports. This allows the ICSP to be
enabled, via the ICSP_MCLR pin, but not stall the WDT if there is no
activity on the interface.
The WDT_Stall[2] is also asserted when the WDT Enable bit in the
ICDCON test register is 0.
11.5 Host Interface
The registers defined for the Watchdog Timer (WDT) are accessible by the embedded controller as indicated in Section
11.8, "EC-Only Registers". All registers accesses are synchronized to the host clock and complete immediately. Regis-
ter reads/writes are not delayed by the 5Hz_Clk.
DS00001956D-page 194
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