MEC1404 Datasheet, PDF (123/572 Pages) Microchip Technology – Keyboard and Embedded Controller Products for Notebook PC

MEC140X/1X
4.9.5 SRAM MEMORY BAR CONFIGURATION
Offset ^A4h
Bits
Description
Type
31:8 RESERVED
7 VALID
If this bit is 1, the SRAM Memory BAR is valid and will participate in
LPC matches. If it is 0 this SRAM Memory BAR is ignored.
6:1 RESERVED
RES
R/W
RES
Default
-
0h
Reset
Event
-
nSIO_
RESET
-
-
4.9.6 DEVICE MEMORY BASE ADDRESS REGISTERS (DEV_MEM_BARS)
Some Logical Devices have a Memory Base Address Register. These Device Memory BARs are located in blocks of
Configuration Registers in Logical Device 0Ch, in the AHB address range 000F_33C0h through 000F_33FFh. The fol-
lowing table defines the generic format used for all of these registers.
Each DEV_MEM_BAR is 48 bits wide. The format of each Device Memory BAR is summarized in Section 4.9.6.1,
"Device Memory Base Address Register Format". An LPC memory request is translated by the Device Memory BAR
into an 8-bit read or write transaction on the AHB bus. The 32-bit LPC memory address is translated into a 32-bit AHB
address.
4.9.6.1 Device Memory Base Address Register Format
Offset ^{See Table 4-15, “Device Memory Base Address Registers,” on page 124}
Bits
Description
47:16 LPC Host Address
These 16 bits are used to match LPC I/O addresses
Type
R/W
15 VALID
R/W
If this bit is 1, the BAR is valid and will participate in LPC matches.
If it is 0 this BAR is ignored
Default
Reset
Event
See
TABLE 4-
15:
See
TABLE 4-
15:
nSIO_
RESET
nSIO_
RESET
14 DEVICE (device)
R
See
nSIO_
This bit combined with FRAME constitute the Logical Device Num-
ber. DEVICE identifies the physical location of the logical device.
TABLE 4- RESET
15:
This bit should always be set to 0.
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