MEC1404 Datasheet, PDF (426/572 Pages) Microchip Technology – Keyboard and Embedded Controller Products for Notebook PC

MEC140X/1X
32.6 Host Interface
The registers defined for the Trace FIFO Debug Port (TFDP) are accessible by the various hosts as indicated in Section
32.11, "EC-Only Registers".
32.7 Power, Clocks and Reset
This section defines the Power, Clock, and Reset parameters of the block.
32.7.1 POWER DOMAINS
VTR
32.7.2
Name
CLOCK INPUTS
Description
This power well sources all of the registers and logic in this block.
Name
48 MHz Ring Oscillator
32.7.3 RESETS
Description
This clock input is used to derive the TFDP Clk.
Name
Description
nSYSRST
This reset signal resets all of the registers and logic in this block.
32.8 Interrupts
There are no interrupts generated from this block.
32.9 Low Power Modes
The Trace FIFO Debug Port (TFDP) may be put into a low power state by the chip’s Power, Clocks, and Reset (PCR)
circuitry.
32.10 Description
The TFDP is a unidirectional (from processor to external world) two-wire serial, byte-oriented debug interface for use
by processor firmware to transmit diagnostic information.
The TFDP consists of the Debug Data Register, Debug Control Register, a Parallel-to-Serial Converter, a Clock/Control
Interface and a two-pin external interface (TFDP Clk, TFDP Data). See .
DS00001956D-page 426
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