MEC1404 Datasheet, PDF (282/572 Pages) Microchip Technology – Keyboard and Embedded Controller Products for Notebook PC

MEC140X/1X
17.11.6 FIFO CONTROL REGISTER
This is a write only register at the same location as the Interrupt Identification Register.
Note: DMA is not supported.
Offset ^02h
Bits
Description
Type
7:6 RECV_FIFO_TRIGGER_LEVEL
W
These bits are used to set the trigger level for the RCVR FIFO
interrupt.
5:4 Reserved
R
3 DMA_MODE_SELECT
W
Writing to this bit has no effect on the operation of the UART. The
RXRDY and TXRDY pins are not available on this chip.
2 CLEAR_XMIT_FIFO
W
Setting this bit to a logic “1” clears all bytes in the XMIT FIFO and
resets its counter logic to “0”. The shift register is not cleared. This
bit is self-clearing.
1 CLEAR_RECv_FIFO
W
Setting this bit to a logic “1” clears all bytes in the RCVR FIFO and
resets its counter logic to “0”. The shift register is not cleared. This
bit is self-clearing.
0 EXRF
W
Enable XMIT and RECV FIFO. Setting this bit to a logic “1” enables
both the XMIT and RCVR FIFOs. Clearing this bit to a logic “0”
disables both the XMIT and RCVR FIFOs and clears all bytes from
both FIFOs. When changing from FIFO Mode to non-FIFO (16450)
mode, data is automatically cleared from the FIFOs. This bit must
be a 1 when other bits in this register are written to or they will not
be properly programmed.
Default
0h
Reset
Event
RESET
-
-
0h
RESET
0h
RESET
0h
RESET
0h
RESET
TABLE 17-7: RECV FIFO TRIGGER LEVELS
Bit 7
0
1
Bit 6
0
1
0
1
RECV FIFO
Trigger Level (BYTES)
1
4
8
14
DS00001956D-page 282
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