MEC1404 Datasheet, PDF (137/572 Pages) Microchip Technology – Keyboard and Embedded Controller Products for Notebook PC

MEC140X/1X
phase, an address phase, a dummy cycle phase and the read phase, can take place as a single operation, with a
single interrupt to firmware when the entire transfer is completed
6.10.3 SPI CLOCK
The SPI output clock is derived from the 48 MHz Ring Oscillator, divided by a value programmed in the CLOCK_DIVIDE
field of the QMSPI Mode Register. Sample frequencies are shown in the following table:
TABLE 6-2: EXAMPLE SPI FREQUENCIES
CLOCK_DIVIDE
SPI Clock Frequency
0
187.5 KHz
1
48 MHz
2
24 MHz
3
16 MHz
6
8 MHz
48
1 MHz
128
375 KHz
255
188.25 KHz
6.10.4 ERROR CONDITIONS
The Quad SPI Master Controller can detect some illegal configurations. When these errors are detected, an error is
signaled via the PROGRAMMING_ERROR status bit. This bit is asserted when any of the following errors are detected:
• Both Receive and the Transmit transfers are enabled when the SPI Master Controller is configured for Dual Data
Rate or Quad Data Rate
• Both Pull-up and Pull-down resistors are enabled on either the Receive data pins or the Transmit data pins
• The transfer length is programmed in bit mode, but the total number of bits is not a multiple of 2 (when the control-
ler is configured for Dual Data Rate) or 4 (when the controller is configured for Quad Data Rate)
• Both the STOP bit and the START bits in the QMSPI Execute Register are set to ‘1’ simultaneously
6.11 EC-Only Registers
The registers listed in the EC-Only Register Summary table are for a single instance of the General Purpose Serial
Peripheral Interface. The addresses of each register listed in this table are defined as a relative offset to the host “Base
Address” defined in the EC-Only Register Base Address Table.
TABLE 6-3: EC-ONLY REGISTER BASE ADDRESS TABLE
Block Instance
Quad Mode Serial
Peripheral Interface
Instance
Number
0
Host
EC
Address Space
32-bit internal
address space
Base Address
0000_5400h
The Base Address indicates where the first register can be accessed in a particular address space for a block instance.
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