MEC1404 Datasheet, PDF (109/572 Pages) Microchip Technology – Keyboard and Embedded Controller Products for Notebook PC

MEC140X/1X
TABLE 4-7: LPC I/O REGISTER MAP (CONTINUED)
Logical Device
BAR LPC
Host Address
Example
BAR LPC
Host
Address
LPC
Address
Mask
Offsets
Claimed
Register Name
ACPI EC2
8 Byte Bound-
ary
0030h
ACPI EC3
8 Byte Bound-
ary
0038h
Port 80 BIOS
Debug Port 0
Port 80 BIOS
Debug Port 1
Any I/O Byte
Address
Any I/O Byte
Address
0080h
0081h
7 BAR+0 ACPI_OS_DATA_BYTE_0
+1 ACPI_OS_DATA_BYTE_1
+2 ACPI_OS_DATA_BYTE_2
+3 ACPI_OS_DATA_BYTE_3
+4 Write: ACPI_OS_COMMAND
Read: OS STATUS OS
+5 OS Byte Control
+6 Reserved
+7 Reserved
7 BAR+0 ACPI_OS_DATA_BYTE_0
+1 ACPI_OS_DATA_BYTE_1
+2 ACPI_OS_DATA_BYTE_2
+3 ACPI_OS_DATA_BYTE_3
+4 Write: ACPI_OS_COMMAND
Read: OS STATUS OS
+5 OS Byte Control
+6 Reserved
+7 Reserved
0 BAR+0 Host Data
0 BAR+0 Host Data
4.8.2.2 Device Memory Transactions
LPC Memory cycles are single byte read or writes that occur in a 32-bit address range. The LPC block will claim a mem-
ory transaction that is targeted for one of these logical devices. A Device Memory Base Address Register has been
implemented for the logical devices listed in Table 4-15, “Device Memory Base Address Registers,” on page 124
On every LPC bus Memory access all Base Address Registers are checked in parallel and if any matches the LPC mem-
ory address the LPC Interface claims the bus cycle. The memory address is claimed as described in I/O Transactions
on page 106 except that the LPC memory cycle address is 32 bits instead of the 16 bit I/O cycle address.
Software should insure that no two BARs map the same LPC memory address. If two BARs do map to the same
address, the BAR_CONFLICT bit in the Host Bus Error Register is set when an LPC access targeting the BAR Conflict
address. An EC interrupt can be generated.
Each Device Memory BAR is 48 bits wide. The format of each Device Memory BAR is summarized in Device Memory
Base Address Register Format. An LPC memory request is translated by the Device Memory BAR into an 8-bit read or
write transaction on the AHB bus. The 32-bit LPC memory address is translated into a 32-bit AHB address.
The Base Address Register Table is itself part of the AHB address space. It resides in the Configuration quadrant of
Logical Device Ch, the LPC Interface.
4.8.2.3 SRAM Memory Transactions
In addition to mapping LPC Memory transactions into Logical Devices, Memory transactions can be mapped into inter-
nal address space, as configured by the SRAM Memory BARs. LPC Memory cycles are single byte read or writes that
occur in a 32-bit address range. The LPC block will claim LPC memory cycles that match the programmed SRAM Mem-
ory BAR Register if the VALID in the SRAM Memory BAR Configuration is set to 1. No memory cycles will be claimed
if this bit is cleared.
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