MEC1404 Datasheet, PDF (121/572 Pages) Microchip Technology – Keyboard and Embedded Controller Products for Notebook PC

MEC140X/1X
Offset ^{See Table 4-14, “I/O Base Address Registers,” on page 122}
Bits
Description
13:8 FRAME
These 6 bits are used to specify a logical device frame number
within a bus. This field is multiplied by 400h to provide the frame
address within the peripheral bus address. Frame values for
frames corresponding to logical devices that are not present on the
device are invalid.
7:0 MASK
These 8 bits are used to mask off address bits in the address
match between an LPC I/O address and the Host Address field of
the BARs, as described in Section 4.8.2.1, "I/O Transactions". A
block of up to 256 8-bit registers can be assigned to one base
address.
Type
R
R
(See
TABLE
4-14:)
Default
See
TABLE 4-
14:
See
TABLE 4-
14:
Reset
Event
Note 4-
11
Note 4-
11
Note 4-11
Note 4-12
Offset 60h is the LPC Base Address register. The LPC Base Address register is only reset on
nSYSRST. All other Base Address Registers are reset on nSIO_RESET.
Bits[31:16] LPC Host Address bit field in the LPC Base Address register at offset 60h must be written
LSB then MSB. This particular register has a shadow that lets the Host come in and write to the lower
byte of the 16-bit address, and the resulting 16-bit LPC Host address field does not update. Writing
to the upper byte triggers a full 16-bit field update.
4.9.3.2 Logical Device IO_BAR Description
The following table defines the IO_BAR of each logical device implemented in the design.
Note: After the VCC_PWRGD signal is asserted, the iRESET_OUT bit of the Power Reset Control
(PWR_RST_CTRL) Register must be cleared by firmware in order to write the BAR registers listed.
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DS00001956D-page 121