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MEC1404 Datasheet, PDF (86/572 Pages) Microchip Technology – Keyboard and Embedded Controller Products for Notebook PC
MEC140X/1X
3.9.5 SYSTEM SLEEP CONTROL REGISTER (SYS_SLP_CNTRL)
Offset 18h
Bits
Description
Type
31:7 RESERVED
6 Auto Clear Sleep
0: Sleep All and Sleep Debug are not cleared by HW when proces-
sor vectors to an interrupt,
1: Sleep All and Sleep Debug will be cleared by HW when the pro-
cessor vectors to an interrupt.
5 Sleep Debug
0: don't keep processor asleep after debug wake,
1: keep processor asleep after a debug wake.
If the Auto Clear Sleep bit is set, HW clears this bit when the pro-
cessor vectors to an interrupt. (same as Sleep All bit). Firmware
must play a role in keeping the processor asleep after a debug
wake. Firmware needs to implement a Do-While loop around the
processors sleep instruction. While this bit is 1, the sleep instruc-
tion must be re-executed.
Note: See Application Note below this table.
4 Sleep All
0: blocks are not commanded to sleep,
1: all blocks are commanded to sleep.
Note: If the Auto Clear Sleep bit is set, HW clears this bit when
the processor vectors to an interrupt.
3 RESERVED
2 Core regulator standby
0: keep regulator fully operational when sleeping.
1: standby the regulator when sleeping. Allows enough power for
chip static operation for memory retention.
Note: See Table 3-12, "System Sleep Control Bit Encoding"
1 Ring oscillator output gate
0: keep ROSC ungated when sleeping.
1: gate the ROSC output when sleeping.
Note: See Table 3-12, "System Sleep Control Bit Encoding"
0 Ring oscillator power down
0: keep ROSC operating when sleeping.
1: disable ROSC when sleeping. Clocks will start on wakeup, but
there is a clock lock latency penalty.
Note: See Table 3-12, "System Sleep Control Bit Encoding"
APPLICATION NOTE: Sample code for Sleep Debug = 1
do {
wait; //processor sleep instruction
} while (sleep_debug == 1);
RES
R/W
R/W
R/W
RES
R/W
R/W
R/W
Default
Reset
Event
0h
nSYSR
ST
0h
nSYSR
ST
0h
nSYSR
ST
0h
nSYSR
ST
0h
nSYSR
ST
0h
nSYSR
ST
DS00001956D-page 86
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