MEC1404 Datasheet, PDF (191/572 Pages) Microchip Technology – Keyboard and Embedded Controller Products for Notebook PC

MEC140X/1X
TABLE 10-9: GIRQX AGGREGATOR CONTROL REGISTER FORMAT (CONTINUED)
Offset ^-
Bits
Description
0 JTEnable (Jump-Table Enable)
0 = aggregated : present only the vector address from bits 17:1
1 = disaggregated/jump-table: present vector address from bits 17:1
+ (vector_spacing)*(winning interrupt source bit position)
Type
R/W
Default
0h
Reset
Event
nSYSR
ST
10.12.3 INTERRUPT PRIORITY CONTROL REGISTERS
TABLE 10-10: GIRQX [N+7:N] INTERRUPT PRIORITY REGISTER FORMAT
Offset ^-
Bits
31:30 Reserved
29:28 GIRQX [N+7] Priority
00 = Priority Level 1
01 = Priority Level 3
10 = Priority Level 5
11 = Priority Level 7
27:26 Reserved
25:24 GIRQX [N+6] Priority
00 = Priority Level 1
01 = Priority Level 3
10 = Priority Level 5
11 = Priority Level 7
23:22 Reserved
21:20 GIRQX [N+5] Priority
00 = Priority Level 1
01 = Priority Level 3
10 = Priority Level 5
11 = Priority Level 7
19:18 Reserved
17:16 GIRQX [N+4] Priority
00 = Priority Level 1
01 = Priority Level 3
10 = Priority Level 5
11 = Priority Level 7
15:14 Reserved
13:12 GIRQX [N+3] Priority
00 = Priority Level 1
01 = Priority Level 3
10 = Priority Level 5
11 = Priority Level 7
11:10 Reserved
Description
Type
R
R/W
R
R/W
R
R/W
R
R/W
R
R/W
R
Default
-
0h
Reset
Event
-
nSYSR
ST
-
-
0h
nSYSR
ST
-
-
0h
nSYSR
ST
-
-
0h
nSYSR
ST
-
-
0h
nSYSR
ST
-
-
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