MEC1404 Datasheet, PDF (357/572 Pages) Microchip Technology – Keyboard and Embedded Controller Products for Notebook PC

MEC140X/1X
24.11.4 DMA CHANNEL N DEVICE ADDRESS REGISTER
Offset ^0Ch
Bits
Description
Type
31:0 DEVICE_ADDRESS
R/W
This is the Master Device address.
This is used as the address that will access the Device on the
DMA. The Device is defined as the Master of the DMA transfer; as
in the device that is controlling the Hardware Flow Control.
APPLICATION NOTE: Only Channel 0 has CRC function which
may be utilized only by the Quad SPI
Master Controller and for Memory-to-
Memory transfers. It is recommended to
use Channels 1-6 for the SMBus
Controllers.
This field is updated by Hardware after every Data Packet transfer
by the size of the transfer, as defined by DMA Channel Con-
trol:Transfer Size while the DMA Channel Control:Increment
Device Address is Enabled.
Note:
This field is only as large as the maximum allowed AHB
Address Size in the system. If the HADDR size is 24
Bits, then Bits [31:24] will be RESERVED.
24.11.5 DMA CHANNEL N CONTROL REGISTER
Offset ^10h
Bits
Description
Type
31:26 Reserved
R
25 TRANSFER_ABORT
R/W
This is used to abort the current transfer on this DMA Channel. The
aborted transfer will be forced to terminate immediately.
24 TRANSFER_GO
R/W
This is used for the Firmware Flow Control DMA transfer.
This is used to start a transfer under the Firmware Flow Control.
Do not use this in conjunction with the Hardware Flow Control;
DMA Channel Control:Disable Hardware Flow Control must be
set in order for this field to function correctly.
23 Reserved
R
22:20 TRANSFER_SIZE
R/W
This is the transfer size in Bytes of each Data Packet transfer.
Note: The transfer size must be a legal transfer size. Valid
sizes are 1, 2 and 4 Bytes.
Default
0000h
Reset
Event
DMA_
RESET
Default
-
0h
Reset
Event
-
DMA_R
ESET
0h
DMA_R
ESET
-
-
0h
DMA_R
ESET
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DS00001956D-page 357