MEC1404 Datasheet, PDF (32/572 Pages) Microchip Technology – Keyboard and Embedded Controller Products for Notebook PC

MEC140X/1X
Power well emulation for GPIOs and for signals that are multiplexed with GPIO signals is controlled by the Power Gating
Signals field in the GPIO Pin Control Register.
2.10.2 PIN MULTIPLEXING TABLE
In the following table, the columns have the following meanings:
MUX
If the pin has an associated GPIO, then the MUX column refers to the Mux Control field in the GPIO Pin Control Register.
Setting the Mux Control field to value listed in the row will configure the pin for the signal listed in the Signal column on
the same row. The row marked “Default” is the setting that is assigned on system reset.
If there is no GPIO associated with a pin, then the pin has a single function.
SIGNAL
This column lists the signals that can appear on each pin, as configured by the MUX control.
BUFFER TYPE
Pin buffer types are defined in Table 42-5, “DC Electrical Characteristics,” on page 494.
Note that all GPIO pins are of buffer type PIO, which may be configured as input/output, push-pull/OD etc. via the GPIO
Pin Control Register and Pin Control Register 2. There are some pins where the buffer type is configured by the alternate
function selection, in which case that buffer type is shown in this column.
DEFAULT BUFFER OPERATION
This column gives the pin behavior following the power-up of VTR. All GPIO pins are programmable after this event.
This default pin behavior corresponds to the row marked “Default” in the MUX column.
SIGNAL POWER WELL
This column defines the power well that powers the pin.
EMULATED POWER WELL
Power well emulation for GPIOs and for signals that are multiplexed with GPIO signals is controlled by the Power Gating
Signals field in the GPIO Pin Control Register. Power well emulation for signals that are not multiplexed with GPIO sig-
nals is defined by the entries in this column. See Section 2.10.1, "VCC Power Domain Emulation".
GATED STATE
This column defines the internal value of an input signal when either its emulated power well is inactive or it is not
selected by the GPIO alternate function MUX. A value of “No Gate” means that the internal signal always follows the
pin even when the emulated power well is inactive.
Note: Gated state is only meaningful to the operation of input signals. A gated state on an output pin defines the
internal behavior of the GPIO MUX and does not imply pin behavior.
TABLE 2-2: MEC140X PIN MULTIPLEXING
VTQFP
Pin#
Mux
Signal Name
1
Default: 0
GPIO157
1
1
LED0
1
2
TST_CLK_OUT
1
3
Reserved
1
Strap
MEC140x
Buffer
Type
PIO
PIO
PIO
Reserved
Default
Buffer
Operation
I-4
Signal
Power
Well
VTR
VTR
VTR
Reserved
Emulated
Power
Well
VTR/VCC
VTR
VTR
Reserved
Gated
State
No Gate
Reserved
Reserved
Notes
Note 13
DS00001956D-page 32
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