MEC1404 Datasheet, PDF (502/572 Pages) Microchip Technology – Keyboard and Embedded Controller Products for Notebook PC

MEC140X/1X
42.3 Power Consumption
TABLE 42-14: VTR SUPPLY CURRENT, I_VTR
VCC
On
VTR
On
LPC
Clock
On
48 MHz
Ring
Oscillator
Frequency
Typical
(3.3V,
25^o C)
Max
(3.45V,
70^o C)
48MHz
10.75 12.50
Units
mA FULL ON
Comments
On
On
On
12MHz
5.50
6.75
mA FULL ON
On
On
On
3MHz
3.55
4.75
mA FULL ON
On
On
On
1MHz
3.25
4.50
mA FULL ON
On
On
On
12MHz
2.85
4.00
mA Heavy Sleep 1
On
On
On
Off
1.05
2.25
mA Heavy Sleep 2
On
On
On
Off
0.75
1.95
mA Heavy Sleep 3
Off
On
Off
48MHz
9.75
11.25
mA FULL ON
Off
On
Off
12MHz
4.50
6.00
mA FULL ON
Off
On
Off
3MHz
2.65
4.00
mA FULL ON
Off
On
Off
1MHz
2.35
3.75
mA FULL ON
Off
On
Off
48MHz
9.50
10.75
mA EC running, all peripherals Off
Off
On
Off
12MHz
4.25
5.50
mA EC running, all peripherals Off
Off
On
Off
3MHz
2.50
3.65
mA EC running, all peripherals Off
Off
On
Off
1MHz
2.25
3.50
mA EC running, all peripherals Off
Off
On
Off
12MHz
2.00
3.25
mA Heavy Sleep 1
Off
On
Off
Off
0.80
2.00
mA Heavy Sleep 2
Off
On
Off
Off
0.52
1.70
mA Heavy Sleep 3
Off
On
Off
Off
0.47
1.65
mA Deepest Sleep
Note 1:
2:
3:
4:
FULL ON is defined as follows: The processor is not sleeping, the Core regulator and the Ring Oscillator
remain powered, and at least one block is not sleeping.
The sleep states are defined in the System Sleep Control Register in the Power, Clocks and Resets
Chapter. See Table 3-12, “System Sleep Control Bit Encoding,” on page 87.
In order to achieve the lowest leakage current when both PECI and SB TSI are not used, set the
VREF_CPU Disable bit to 1. This bit is defined in Section 34.8.5, VREF_CPU DISABLE.
All values are taken with DAC 0, Comparator 0, DAC 1, Comparator 1, ADC all disabled. See Table 42-15
for additional I_VTR with these blocks enabled.
DS00001956D-page 502
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