MEC1404 Datasheet, PDF (442/572 Pages) Microchip Technology – Keyboard and Embedded Controller Products for Notebook PC

MEC140X/1X
35.0 VBAT REGISTER BANK
35.1 Introduction
This chapter defines a bank of registers powered by VBAT.
35.2 Interface
This block is designed to be accessed internally by the EC via the register interface.
35.3 Power, Clocks and Reset
This section defines the Power, Clock, and Reset parameters of the block.
35.3.1 POWER DOMAINS
Name
Description
VBAT
The VBAT Register Bank are all implemented on this single power
domain.
35.3.2 CLOCK INPUTS
This block does not require any special clock inputs. All register accesses are synchronized to the host clock.
35.3.3 RESETS
VBAT_POR
Name
35.4 Interrupts
Description
This reset signal, which is an input to this block, resets all the logic and
registers to their initial default state.
Name
Description
PFR_Status
This interrupt signal from the Power-Fail and Reset Status Register
indicates VBAT RST and WDT events.
35.5 Low Power Modes
The VBAT Register Bank is designed to always operate in the lowest power consumption state.
35.6 Description
The VBAT Register Bank block is a block implemented for aggregating miscellaneous battery-backed registers required
the host and by the Embedded Controller (EC) Subsystem that are not unique to a block implemented in the EC sub-
system.
DS00001956D-page 442
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