MEC1404 Datasheet, PDF (360/572 Pages) Microchip Technology – Keyboard and Embedded Controller Products for Notebook PC

MEC140X/1X
24.11.6 DMA CHANNEL N INTERRUPT STATUS REGISTER
Offset ^14h
Bits
Description
Type
7:3 Reserved
2 STATUS_DONE
This is an interrupt source register.
This flags when the DMA Channel has completed a transfer suc-
cessfully on its side.
A completed transfer is defined as when the DMA Channel
reaches its limit; Memory Start Address equals Memory End
Address.
A completion due to a Hardware Flow Control Terminate will not
flag this interrupt.
R
R/WC
1=Memory Start Address equals Memory End Address
1=Memory Start Address does not equal Memory End Address
1 STATUS_FLOW_CONTROL
This is an interrupt source register.
This flags when the DMA Channel has encountered a Hardware
Flow Control Request after the DMA Channel has completed the
transfer. This means the Master Device is attempting to overflow
the DMA.
1=Hardware Flow Control is requesting after the transfer has com-
pleted
0=No Hardware Flow Control event
0 STATUS_BUS_ERROR
This is an interrupt source register.
This flags when there is an Error detected over the internal 32-bit
Bus.
R/WC
1: Error detected.
24.11.7 DMA CHANNEL N INTERRUPT ENABLE REGISTER
Default
-
0h
Reset
Event
-
DMA_
RESET
0h
DMA_
RESET
0h
DMA_
RESET
Offset ^18h
Bits
Description
7:3 Reserved
2 STATUS_ENABLE_DONE
This is an interrupt enable for DMA Channel Interrupt:Status
Done.
1=Enable Interrupt
0=Disable Interrupt
Type
R
R/W
Default
-
0h
Reset
Event
-
DMA_
RESET
DS00001956D-page 360
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