MEC1404 Datasheet, PDF (6/572 Pages) Microchip Technology – Keyboard and Embedded Controller Products for Notebook PC

MEC140X/1X
1.0 GENERAL DESCRIPTION
The MEC140X/1X is a family of keyboard and embedded controller designs customized for notebooks and tablet plat-
forms. The MEC140X/1X family is a highly-configurable, mixed signal, advanced I/O controller architecture. Every
device in the family incorporates a 32-bit MIPS32 M14K Microcontroller core with a closely-coupled SRAM for code and
data. A secure boot-loader is used to download the custom firmware image from the system’s shared SPI Flash device,
thereby allowing system designers to customize the device’s behavior.
The MEC140X/1X products may be configured to communicate with the system host through one of three host inter-
faces: Intel Low Pin Count (LPC), eSPI, or I2C. Note that this functionality is product dependent. To see which features
apply to a specific part in the family see Products on page 3. The document defines the features for all devices in the
family.
The MEC140X/1X products are designed to operate as either a stand-alone I/O device or as an EC Base Component
of a split-architecture Advanced I/O Controller system which uses BC-Link communication protocol to access up to two
BC bus companion components. The BC-Link protocol is peer-to-peer providing communication between the
MEC140X/1X embedded controller and registers located in a companion device.
The MEC140X/1X is directly powered by a minimum of two separate suspend supply planes (VBAT and VTR) and
senses a third runtime power plane (VCC) to provide “instant on’ and system power management functions. In addition,
this family of products has the option to connect the VTR_33_18 power pin to either a 3.3V VTR power supply or a 1.8V
power supply. This option may only be used with the eSPI Host Interface or the I2C Host Interface. In systems using the
I2C Host Interface, ten GPIOs are powered by VTR_33_18, thereby allowing them to operate at either 3.3V or 1.8V. All
the devices are equipped with a Power Management Interface that supports low-power states and are capable of oper-
ating in a Connected Standby system.
The MEC140X/1X family of devices offer a software development system interface that includes a Trace FIFO Debug
port, a host accessible serial debug port with a 16C550A register interface, a Port 80 BIOS Debug Port, and an In-circuit
Serial Programming (ICSP) interface.
1.1 Boot ROM
Following the release of the EC_PROC_RESET# signal, the processor will start executing code in the Boot ROM. The
Boot ROM executes the SPI Flash Loader, which downloads User Code from an external SPI Flash and stores it in the
internal Code RAM. Upon completion, the Boot ROM jumps into the User Code and starts executing.
1.2 Initialize Host Interface
By default, this device powers up all the interfaces, except the VBAT powered interfaces and select signals, to GPIO
inputs. The Boot ROM is used to download code from an external flash via either the Shared Flash Interface, the eSPI
flash channel or the Private Flash Interface. The downloaded code must configure the device’s pins according to the
platform’s needs. This includes initializing the Host Interface.
Once the device is configured for operation, the downloaded code must deassert the system’s RSMRST# (Resume
Reset) signal. Any GPIO may be selected for the RSMRST# function. This is up to the system board designer. The only
requirement is that the board designer attach an external pull-down on the GPIO pin being used for the RSMRST# func-
tion. This will ensure the RSMRST# pin is asserted low by default and does not glitch during power-up.
This family of devices has up to three Host Interface options. It may be configured as an LPC Device, an eSPI Device,
or I2C device. See Products on page 3 for the features supported in each device.
On a VTR POR, all the host interface pins default to GPIO inputs.
1.2.1 CONFIGURE LPC INTERFACE
The downloaded firmware must configure the GPIO Pin Control registers for the LPC alternate function, configure the
LPC Base Address Register (BAR), and activate the LPC block.
Example:
• GPIO034 Pin Control Register = 0x1000;
• GPIO040 Pin Control Register = 0x1000;
• GPIO041 Pin Control Register = 0x1000;
• GPIO042 Pin Control Register = 0x1000;
• GPIO043 Pin Control Register = 0x1000;
• GPIO044 Pin Control Register = 0x1000;
//ALT FUNC1 – PCI_CLK
//ALT FUNC1 – LAD0
//ALT FUNC1 – LAD1
//ALT FUNC1 – LAD2
//ALT FUNC1 – LAD3
//ALT FUNC1 – LFRAME_N
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