MEC1404 Datasheet, PDF (163/572 Pages) Microchip Technology – Keyboard and Embedded Controller Products for Notebook PC

MEC140X/1X
9.0 MEMORY ORGANIZATION
The MEC140X/1X implements two address spaces: Virtual and Physical. All hardware resources such as program
memory, data memory and peripherals are located at their respective physical addresses. Virtual addresses are exclu-
sively used by the CPU to fetch and execute instructions as well as access peripherals. Physical addresses are used
by peripherals such as the Internal DMA Controller that access memory independently of CPU.
The following table lists all the defined memory regions in the 4 GB EC Address Space. Accessing undefined memory
regions may cause unwanted results, such as a memory exception.
TABLE 9-1: EC ADDRESS SPACE
Location
Space
Virtual Start
Address
Physical Start
Address
Physical End
Address
Size
CC-MMCR
(Note 1)
KSEG1
0xBFFF_C000
0x1FFF_C000
0x1FFF_FFFF
16 kB
Data RAM
KSEG1
0xBFD1_8000
0x1FD1_8000
0x1FD1_FFFF
32 kB
(Note 4)
Code RAM
(Note 3)
KSEG1
0xBFD0_0000
0xBFCF_8000
0xBFCF_0000
0x1FD0_0000
0x1FCF_8000
0x1FCF_0000
0x1FD1_7FFF
96 kB
128 kB
160 kB
(Note 5)
Boot ROM
KSEG1
0xBFC0_0000
0x1FC0_0000
0x1FC0_FFFF
64 kB
MMCR (Note 2) KSEG1
0xA000_0000
0x0000_0000
0x001F_FFFF
2 MB
Note 1: CC-MMCR = closely-coupled memory-mapped control registers, i.e. interrupt registers (JTVIC).
2: MMCR = memory-mapped control registers, i.e. all the peripheral registers.
3: The IRQ EBASE must be programmed at BFD0_0000h in order to be on a 256k byte boundary. All IRQ
routine entry points must be located above this address.
4: 32kB is the default Data RAM size; however, other sizes of Data RAM can be used (for example 8kB or
16kB) with the remainder used as Code RAM. See the MEC14xx Programmers Reference Guide for con-
figuring the different settings.
5: The size of the code RAM is part dependent.
The embedded controller executes code out of the EC Instruction Memory via the closely-coupled ISRAM Interface. The
Code RAM, Boot ROM and Debug RAM are all accessible as EC Instruction Memory. Data references can come from
either the EC Data Memory via the closely-coupled DSRAM Interface (i.e., Data RAM access) or from any address
located in the EC Address Space via the System Interface.
The Code and Data SRAM is optimized to the memory allocation shown in the table. This allows code and data
accesses to happen simultaneously. However, software may use Code RAM for data and Data RAM for code. The only
penalty will be access time. When the ISRAM and DSRAM interfaces both attempt to access the same memory region
the accesses become serialized.
Example:
The 128KBytes SRAM (Code or Data) memory is allocated as follows:
• 96 kB Optimized for Code
• 32 kB Optimized for Data.
A user may choose to organize their code and data space as follows:
STACK
8 kB
DATA
20 kB
CODE
100 kB
Notice that although the Code Space is optimized for 96 kB the user can choose to allocate part of the data memory for
code. The only difference will be the access time for the code implemented in the data space since code and data
accesses will become serialized in that range.
 2015 - 2016 Microchip Technology Inc.
DS00001956D-page 163