MEC1404 Datasheet, PDF (76/572 Pages) Microchip Technology – Keyboard and Embedded Controller Products for Notebook PC

MEC140X/1X
3.7 Chip Power Management Features
This device is designed to always operate in its lowest power state during normal operation. In addition, this device
offers additional programmable options to put individual logical blocks to sleep as defined in Section 3.7.1, "Block Low
Power Modes," on page 76 and to gate off or power down the internal oscillator as described in Section 3.7.2, "Config-
uring the Chip’s Sleep States," on page 76.
3.7.1 BLOCK LOW POWER MODES
All power related control signals are generated and monitored centrally in the chip’s Power, Clocks, and Resets (PCR)
block. The power manager of the PCR block uses a sleep interface to communicate with all the blocks. The sleep inter-
face consists of three signals:
• sleep_en (request to sleep the block) is generated by the PCR block. A group of sleep_en signals are gener-
ated for every clock segment. Each group consists of a sleep_en signal for every block in that clock segment.
• clk_req (request clock on) is generated by every block. They are grouped by blocks on the same clock segment.
The PCR monitors these signals to see when it can gate off clocks.
• reset_en (reset on sleep) bits determine if the block (including registers) will be reset when it enters sleep mode.
A block can always drive clk_req low synchronously, but it MUST drive it high asynchronously since its internal clocks
are gated and it has to assume that the clock input itself is gated. Therefore the block can only drive clk_req high as a
result of a register access or some other input signal.
The following table defines a block’s power management protocol:
Power State
Normal operation
Normal operation
Request sleep
Request sleep
Register Access
sleep_en clk_req
Description
Low
Low Block is idle and NOT requesting clocks. The block gates its
own internal clock.
Low
High Block is NOT idle and requests clocks.
Rising Edge Low Block is IDLE and enters sleep mode immediately. The
block gates its own internal clock. The block cannot request
clocks again until sleep_en goes low.
Rising Edge
High then
Low
Block is not IDLE and will stop requesting clocks and enter
sleep when it finishes what it is doing. This delay is block
specific, but should be less than 1 ms. The block gates its
own internal clock. After driving clk_req low, the block can-
not request clocks again until sleep_en goes low.
X
High Register access to a block is always available regardless of
sleep_en. Therefore the block ungates its internal clock and
drives clk_req high during the access. The block will regate
its internal clock and drive clk_req low when the access is
done.
A wake event clears all sleep enable bits momentarily, and then returns the sleep enable bits back to their original state.
The block that needs to respond to the wake event will do so. See Section 10.11.3, "Wake-Capable Interrupt Events,"
on page 167.
The Sleep Enable, Clock Required and Reset Enable registers are defined in Section 3.8, "EC-Only Registers," on
page 78.
3.7.2 CONFIGURING THE CHIP’S SLEEP STATES
The chip supports four sleep states: SYSTEM HEAVY SLEEP 1, SYSTEM HEAVY SLEEP 2, SYSTEM HEAVY SLEEP
3, SYSTEM DEEPEST SLEEP. The chip will enter one of these four sleep states only when all the blocks have been
commanded to sleep and none of them require the 48 MHz Ring Oscillator (i.e., all clock required status bits = 0), and
the processor has executed its sleep instruction. These sleep states must be selected by firmware via the System Sleep
Control bits implemented in the System Sleep Control Register (SYS_SLP_CNTRL) on page 86 prior to issuing the
sleep instruction. Table 3-12, “System Sleep Control Bit Encoding,” on page 87 defines each of these sleep states.
DS00001956D-page 76
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